forked from OSchip/llvm-project
129 lines
4.5 KiB
YAML
129 lines
4.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
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# Note: 16-bit instructions generally produce a 0 result in the high 16-bits on GFX8 and GFX9 and preserve high 16 bits on GFX10+
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---
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name: add_s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: add_s16
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
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; GFX10-LABEL: name: add_s16
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; GFX10: liveins: $vgpr0, $vgpr1
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; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX10: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_ADD %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: add_s16_zext_to_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: add_s16_zext_to_s32
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
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; GFX10-LABEL: name: add_s16_zext_to_s32
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; GFX10: liveins: $vgpr0, $vgpr1
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; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_ADD_U16_e64_]], 0, 16, implicit $exec
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; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_ADD %2, %3
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%5:vgpr(s32) = G_ZEXT %4
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S_ENDPGM 0, implicit %5
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...
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---
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name: add_s16_neg_inline_const_64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GFX6-LABEL: name: add_s16_neg_inline_const_64
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; GFX6: liveins: $vgpr0
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
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; GFX10-LABEL: name: add_s16_neg_inline_const_64
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; GFX10: liveins: $vgpr0
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; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
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; GFX10: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_CONSTANT i16 -64
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%3:vgpr(s16) = G_ADD %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: add_s16_neg_inline_const_64_zext_to_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
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; GFX6: liveins: $vgpr0
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
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; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
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; GFX10: liveins: $vgpr0
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; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
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; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_SUB_U16_e64_]], 0, 16, implicit $exec
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; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_CONSTANT i16 -64
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%3:vgpr(s16) = G_ADD %1, %2
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%4:vgpr(s32) = G_ZEXT %3
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S_ENDPGM 0, implicit %4
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...
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