forked from OSchip/llvm-project
190 lines
7.1 KiB
C++
190 lines
7.1 KiB
C++
//===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Lanai implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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#define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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#include "LanaiRegisterInfo.h"
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#include "MCTargetDesc/LanaiMCTargetDesc.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "LanaiGenInstrInfo.inc"
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namespace llvm {
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class LanaiInstrInfo : public LanaiGenInstrInfo {
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const LanaiRegisterInfo RegisterInfo;
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public:
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LanaiInstrInfo();
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// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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// such, whenever a client has an instance of instruction info, it should
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// always be able to get register info as well (through this method).
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virtual const LanaiRegisterInfo &getRegisterInfo() const {
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return RegisterInfo;
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}
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bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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const MachineInstr &MIb,
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AliasAnalysis *AA) const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
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const DebugLoc &DL, unsigned DestinationRegister,
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unsigned SourceRegister, bool KillSource) const override;
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void
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storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator Position,
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unsigned SourceRegister, bool IsKill, int FrameIndex,
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const TargetRegisterClass *RegisterClass,
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const TargetRegisterInfo *RegisterInfo) const override;
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void
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loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator Position,
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unsigned DestinationRegister, int FrameIndex,
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const TargetRegisterClass *RegisterClass,
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const TargetRegisterInfo *RegisterInfo) const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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bool getMemOperandWithOffset(const MachineInstr &LdSt,
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const MachineOperand *&BaseOp,
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int64_t &Offset,
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const TargetRegisterInfo *TRI) const override;
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bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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const MachineOperand *&BaseOp,
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int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock,
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MachineBasicBlock *&FalseBlock,
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SmallVectorImpl<MachineOperand> &Condition,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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// For a comparison instruction, return the source registers in SrcReg and
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// SrcReg2 if having two register operands, and the value it compares against
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// in CmpValue. Return true if the comparison instruction can be analyzed.
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bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const override;
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// See if the comparison instruction can be converted into something more
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// efficient. E.g., on Lanai register-register instructions can set the flag
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// register, obviating the need for a separate compare.
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bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const override;
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// Analyze the given select instruction, returning true if it cannot be
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// understood. It is assumed that MI->isSelect() is true.
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//
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// When successful, return the controlling condition and the operands that
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// determine the true and false result values.
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//
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// Result = SELECT Cond, TrueOp, FalseOp
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//
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// Lanai can optimize certain select instructions, for example by predicating
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// the instruction defining one of the operands and sets Optimizable to true.
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bool analyzeSelect(const MachineInstr &MI,
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SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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unsigned &FalseOp, bool &Optimizable) const override;
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// Given a select instruction that was understood by analyzeSelect and
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// returned Optimizable = true, attempt to optimize MI by merging it with one
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// of its operands. Returns NULL on failure.
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//
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// When successful, returns the new select instruction. The client is
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// responsible for deleting MI.
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//
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// If both sides of the select can be optimized, the TrueOp is modifed.
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// PreferFalse is not used.
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MachineInstr *optimizeSelect(MachineInstr &MI,
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SmallPtrSetImpl<MachineInstr *> &SeenMIs,
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bool PreferFalse) const override;
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bool reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Condition) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
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MachineBasicBlock *FalseBlock,
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ArrayRef<MachineOperand> Condition,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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};
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static inline bool isSPLSOpcode(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::LDBs_RI:
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case Lanai::LDBz_RI:
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case Lanai::LDHs_RI:
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case Lanai::LDHz_RI:
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case Lanai::STB_RI:
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case Lanai::STH_RI:
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return true;
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default:
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return false;
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}
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}
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static inline bool isRMOpcode(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::LDW_RI:
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case Lanai::SW_RI:
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return true;
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default:
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return false;
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}
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}
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static inline bool isRRMOpcode(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::LDBs_RR:
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case Lanai::LDBz_RR:
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case Lanai::LDHs_RR:
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case Lanai::LDHz_RR:
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case Lanai::LDWz_RR:
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case Lanai::LDW_RR:
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case Lanai::STB_RR:
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case Lanai::STH_RR:
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case Lanai::SW_RR:
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return true;
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default:
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return false;
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}
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}
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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