forked from OSchip/llvm-project
333 lines
13 KiB
TableGen
333 lines
13 KiB
TableGen
//===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'D',
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// Double-Precision Floating-Point instruction set extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>,
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SDTCisVT<1, i32>,
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SDTCisVT<2, f64>]>;
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def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>;
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def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPFMAD_rrr_frm<RISCVOpcode opcode, string opcodestr>
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: RVInstR4<0b01, opcode, (outs FPR64:$rd),
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(ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3),
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opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
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class FPFMADDynFrmAlias<FPFMAD_rrr_frm Inst, string OpcodeStr>
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: InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
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(Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
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(ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPALUD_rr_frm<bits<7> funct7, string opcodestr>
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: RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd),
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(ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr,
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"$rd, $rs1, $rs2, $funct3">;
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class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr>
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: InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
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(Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPCmpD_rr<bits<3> funct3, string opcodestr>
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: RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
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(ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtD] in {
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
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(ins GPR:$rs1, simm12:$imm12),
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"fld", "$rd, ${imm12}(${rs1})">;
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// Operands for stores are in the order srcreg, base, offset rather than
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// reflecting the order these fields are specified in the instruction
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// encoding.
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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def FSD : RVInstS<0b011, OPC_STORE_FP, (outs),
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(ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
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"fsd", "$rs2, ${imm12}(${rs1})">;
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def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">;
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def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">;
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def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">;
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def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">;
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def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">;
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def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">;
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def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">;
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def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">;
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def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">;
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def : FPALUDDynFrmAlias<FADD_D, "fadd.d">;
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def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">;
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def : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
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def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">;
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def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">;
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def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">;
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def : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">;
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def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d"> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;
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def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">;
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def FSGNJN_D : FPALUD_rr<0b0010001, 0b001, "fsgnjn.d">;
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def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">;
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def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">;
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def FMAX_D : FPALUD_rr<0b0010101, 0b001, "fmax.d">;
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def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d"> {
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let rs2 = 0b00001;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>;
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def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s"> {
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let rs2 = 0b00000;
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}
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def FEQ_D : FPCmpD_rr<0b010, "feq.d">;
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def FLT_D : FPCmpD_rr<0b001, "flt.d">;
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def FLE_D : FPCmpD_rr<0b000, "fle.d">;
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def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d"> {
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let rs2 = 0b00000;
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}
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def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d"> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
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def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d"> {
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let rs2 = 0b00001;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
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def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> {
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let rs2 = 0b00000;
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}
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def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> {
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let rs2 = 0b00001;
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}
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} // Predicates = [HasStdExtD]
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let Predicates = [HasStdExtD, IsRV64] in {
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def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d"> {
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let rs2 = 0b00010;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_L_D, "fcvt.l.d", GPR, FPR64>;
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def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d"> {
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let rs2 = 0b00011;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>;
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def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d"> {
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let rs2 = 0b00000;
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}
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def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l"> {
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let rs2 = 0b00010;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_D_L, "fcvt.d.l", FPR64, GPR>;
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def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu"> {
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let rs2 = 0b00011;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>;
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def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x"> {
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let rs2 = 0b00000;
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}
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} // Predicates = [HasStdExtD, IsRV64]
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtD] in {
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// TODO fld
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// TODO fsd
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def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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// fgt.d/fge.d are recognised by the GNU assembler but the canonical
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// flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
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def : InstAlias<"fgt.d $rd, $rs, $rt",
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(FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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def : InstAlias<"fge.d $rd, $rs, $rt",
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(FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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} // Predicates = [HasStdExtD]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
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: Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
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class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
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: Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;
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let Predicates = [HasStdExtD] in {
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/// Float conversion operations
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// f64 -> f32, f32 -> f64
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def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
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def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
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// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
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// are defined later.
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/// Float arithmetic operations
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def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
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def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
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def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
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def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
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def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
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def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
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def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
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def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
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def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
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// fmadd: rs1 * rs2 + rs3
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def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
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(FMADD_D $rs1, $rs2, $rs3, 0b111)>;
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// fmsub: rs1 * rs2 - rs3
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def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
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(FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// fnmsub: -rs1 * rs2 + rs3
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def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
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(FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// fnmadd: -rs1 * rs2 - rs3
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def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
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(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
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// canonical NaN when giving a signaling NaN. This doesn't match the LLVM
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// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
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// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
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// matches LLVM's fminnum and fmaxnum
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// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
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def : PatFpr64Fpr64<fminnum, FMIN_D>;
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def : PatFpr64Fpr64<fmaxnum, FMAX_D>;
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/// Setcc
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def : PatFpr64Fpr64<seteq, FEQ_D>;
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def : PatFpr64Fpr64<setoeq, FEQ_D>;
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def : PatFpr64Fpr64<setlt, FLT_D>;
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def : PatFpr64Fpr64<setolt, FLT_D>;
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def : PatFpr64Fpr64<setle, FLE_D>;
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def : PatFpr64Fpr64<setole, FLE_D>;
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// Define pattern expansions for setcc operations which aren't directly
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// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
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// Legalizer.
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def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
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(SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
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(FEQ_D FPR64:$rs2, FPR64:$rs2)),
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1)>;
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def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
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/// Loads
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defm : LdPat<load, FLD>;
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/// Stores
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defm : StPat<store, FSD, FPR64>;
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/// Pseudo-instructions needed for the soft-float ABI with RV32D
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// Moves two GPRs to an FPR.
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let usesCustomInserter = 1 in
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def BuildPairF64Pseudo
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: Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2),
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[(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
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// Moves an FPR to two GPRs.
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let usesCustomInserter = 1 in
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def SplitF64Pseudo
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: Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
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[(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
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} // Predicates = [HasStdExtD]
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let Predicates = [HasStdExtD, IsRV32] in {
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// double->[u]int. Round-to-zero must be used.
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def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_W_D FPR64:$rs1, 0b001)>;
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def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>;
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// [u]int->double.
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def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_W GPR:$rs1)>;
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def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>;
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} // Predicates = [HasStdExtD, IsRV32]
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let Predicates = [HasStdExtD, IsRV64] in {
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def : Pat<(bitconvert GPR:$rs1), (FMV_D_X GPR:$rs1)>;
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def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>;
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// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
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// because fpto[u|s]i produce poison if the value can't fit into the target.
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// We match the single case below because fcvt.wu.d sign-extends its result so
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// is cheaper than fcvt.lu.d+sext.w.
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def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR64:$rs1)), i32),
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(FCVT_WU_D $rs1, 0b001)>;
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// [u]int32->fp
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def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_D_W $rs1)>;
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def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_D_WU $rs1)>;
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def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_L_D FPR64:$rs1, 0b001)>;
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def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_LU_D FPR64:$rs1, 0b001)>;
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// [u]int64->fp. Match GCC and default to using dynamic rounding mode.
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def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_L GPR:$rs1, 0b111)>;
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def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_LU GPR:$rs1, 0b111)>;
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} // Predicates = [HasStdExtD, IsRV64]
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