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llvm-project/llvm/test/MC
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Stanislav Mekhanoshin 6ddadf9901 [AMDGPU] flat scratch ST addressing mode on gfx10 
GFX10 enables third addressing mode for flat scratch instructions,
an ST mode. In that mode both register operands are omitted and
only swizzled offset is used in addition to flat_scratch base.

Differential Revision: https://reviews.llvm.org/D89501
 		2020-10-19 15:29:52 -07:00
..
AArch64 [AArch64] Implement .variant_pcs directive 2020-10-13 10:06:27 +00:00
AMDGPU [AMDGPU] flat scratch ST addressing mode on gfx10 2020-10-19 15:29:52 -07:00
ARM llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits 2020-10-04 15:48:57 -07:00
AVR [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex 2020-07-12 08:14:52 -07:00
AsmParser Introduce and use a new section type for the bb_addr_map section. 2020-10-08 11:13:19 -07:00
BPF [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
COFF [test][MC] Use %python in llvm/test/MC/COFF/bigobj.py 2020-10-07 14:03:28 -04:00
Disassembler [AMDGPU] flat scratch ST addressing mode on gfx10 2020-10-19 15:29:52 -07:00
ELF Show register names in DWARF unwind info. 2020-10-05 15:34:33 -07:00
Hexagon [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Lanai [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
MSP430 [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
MachO llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits 2020-10-04 15:48:57 -07:00
Mips Show register names in DWARF unwind info. 2020-10-05 15:34:33 -07:00
PowerPC [PowerPC] Add outer product instructions for MMA 2020-09-30 18:06:49 -05:00
RISCV [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV. 2020-10-02 17:20:34 +08:00
Sparc [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [SystemZAsmParser] Treat VR128 separately in ParseDirectiveInsn(). 2020-10-06 14:42:40 +02:00
VE [VE] Add VBRD/VMV instructions 2020-10-19 18:33:54 +09:00
WebAssembly [WebAssembly] Prototype i8x16.popcnt 2020-10-15 21:18:22 +00:00
X86 [X86] Add HRESET instruction. 2020-10-13 08:47:26 +08:00