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Simon Pilgrim 8bd2d8780a [DAGCombine] (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) 
We already have a combine for this pattern when the input to shl is add, so we just need to enable the transformation when the input is or.

Original patch by @tstellar

Differential Revision: https://reviews.llvm.org/D19325

llvm-svn: 313251
 		2017-09-14 10:38:30 +00:00
..
AArch64 Revert r312719 "[MachineCombiner] Update instruction depths incrementally for large BBs." 2017-09-13 23:23:09 +00:00
AMDGPU [DAGCombine] (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) 2017-09-14 10:38:30 +00:00
ARC [ARC] Add ARC backend. 2017-08-24 15:40:33 +00:00
ARM Revert r313009 "[ARM] Use ADDCARRY / SUBCARRY" 2017-09-12 16:24:17 +00:00
AVR [AVR] Enable the '__do_copy_data' function 2017-09-11 10:32:51 +00:00
BPF bpf: add " ll" in the LD_IMM64 asmstring 2017-09-11 23:43:35 +00:00
Generic [MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0 2017-09-01 22:17:14 +00:00
Hexagon Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnits 2017-09-08 16:29:50 +00:00
Inputs
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Lanai
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MIR AMDGPU: Handle non-temporal loads and stores 2017-09-07 17:14:54 +00:00
MSP430 [DAG] Improve Aliasing of operations to static alloca 2017-07-18 20:06:24 +00:00
Mips [XRay][CodeGen] Use the current function symbol as the associated symbol for the instrumentation map 2017-09-14 07:08:23 +00:00
NVPTX [CUDA] Added rudimentary support for CUDA-9 and sm_70. 2017-09-07 18:14:32 +00:00
Nios2
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PowerPC [XRay][CodeGen] Use the current function symbol as the associated symbol for the instrumentation map 2017-09-14 07:08:23 +00:00
SPARC Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"" 2017-09-04 15:47:00 +00:00
SystemZ Move llvm/test/CodeGen/X86/clear-liverange-spillreg.mir to SystemZ. It was in wrong place. 2017-09-14 00:03:23 +00:00
Thumb Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"" 2017-09-04 15:47:00 +00:00
Thumb2 [ARM] Call setBooleanContents(ZeroOrOneBooleanContent) 2017-08-22 11:02:37 +00:00
WebAssembly [WebAssembly] Add sign extend instructions from atomics proposal 2017-09-13 00:29:06 +00:00
WinEH
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X86 [DAGCombine] (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) 2017-09-14 10:38:30 +00:00
XCore Delete Default and JITDefault code models 2017-08-03 02:16:21 +00:00