forked from OSchip/llvm-project
978 lines
36 KiB
C++
978 lines
36 KiB
C++
//===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple two pass scheduler. The first pass attempts to push
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// backward any lengthy instructions and critical paths. The second pass packs
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// instructions into semi-optimal time slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) {
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TII = TM.getInstrInfo();
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MRI = TM.getRegisterInfo();
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ConstPool = BB->getParent()->getConstantPool();
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}
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/// CheckForPhysRegDependency - Check if the dependency between def and use of
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/// a specified operand is a physical register dependency. If so, returns the
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/// register and the cost of copying the register.
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static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op,
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const MRegisterInfo *MRI,
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const TargetInstrInfo *TII,
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unsigned &PhysReg, int &Cost) {
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if (Op != 2 || Use->getOpcode() != ISD::CopyToReg)
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return;
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unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(Reg))
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return;
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unsigned ResNo = Use->getOperand(2).ResNo;
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if (Def->isTargetOpcode()) {
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const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
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if (ResNo >= II.getNumDefs() &&
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II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
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PhysReg = Reg;
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const TargetRegisterClass *RC =
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MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
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Cost = RC->getCopyCost();
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}
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}
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}
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SUnit *ScheduleDAG::Clone(SUnit *Old) {
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SUnit *SU = NewSUnit(Old->Node);
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for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i)
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SU->FlaggedNodes.push_back(SU->FlaggedNodes[i]);
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SU->InstanceNo = SUnitMap[Old->Node].size();
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SU->Latency = Old->Latency;
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SU->isTwoAddress = Old->isTwoAddress;
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SU->isCommutable = Old->isCommutable;
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SU->hasPhysRegDefs = Old->hasPhysRegDefs;
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SUnitMap[Old->Node].push_back(SU);
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return SU;
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}
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/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
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/// This SUnit graph is similar to the SelectionDAG, but represents flagged
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/// together nodes with a single SUnit.
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void ScheduleDAG::BuildSchedUnits() {
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// Reserve entries in the vector for each of the SUnits we are creating. This
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// ensure that reallocation of the vector won't happen, so SUnit*'s won't get
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// invalidated.
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SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
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for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
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E = DAG.allnodes_end(); NI != E; ++NI) {
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if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
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continue;
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// If this node has already been processed, stop now.
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if (SUnitMap[NI].size()) continue;
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SUnit *NodeSUnit = NewSUnit(NI);
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// See if anything is flagged to this node, if so, add them to flagged
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// nodes. Nodes can have at most one flag input and one flag output. Flags
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// are required the be the last operand and result of a node.
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// Scan up, adding flagged preds to FlaggedNodes.
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SDNode *N = NI;
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if (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
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do {
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N = N->getOperand(N->getNumOperands()-1).Val;
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NodeSUnit->FlaggedNodes.push_back(N);
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SUnitMap[N].push_back(NodeSUnit);
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} while (N->getNumOperands() &&
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N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
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std::reverse(NodeSUnit->FlaggedNodes.begin(),
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NodeSUnit->FlaggedNodes.end());
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}
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// Scan down, adding this node and any flagged succs to FlaggedNodes if they
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// have a user of the flag operand.
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N = NI;
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while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
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SDOperand FlagVal(N, N->getNumValues()-1);
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// There are either zero or one users of the Flag result.
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bool HasFlagUse = false;
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for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
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UI != E; ++UI)
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if (FlagVal.isOperand(*UI)) {
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HasFlagUse = true;
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NodeSUnit->FlaggedNodes.push_back(N);
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SUnitMap[N].push_back(NodeSUnit);
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N = *UI;
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break;
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}
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if (!HasFlagUse) break;
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}
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// Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
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// Update the SUnit
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NodeSUnit->Node = N;
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SUnitMap[N].push_back(NodeSUnit);
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ComputeLatency(NodeSUnit);
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}
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// Pass 2: add the preds, succs, etc.
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for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
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SUnit *SU = &SUnits[su];
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SDNode *MainNode = SU->Node;
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if (MainNode->isTargetOpcode()) {
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unsigned Opc = MainNode->getTargetOpcode();
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const TargetInstrDesc &TID = TII->get(Opc);
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for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
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if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
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SU->isTwoAddress = true;
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break;
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}
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}
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if (TID.isCommutable())
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SU->isCommutable = true;
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}
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// Find all predecessors and successors of the group.
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// Temporarily add N to make code simpler.
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SU->FlaggedNodes.push_back(MainNode);
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for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
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SDNode *N = SU->FlaggedNodes[n];
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if (N->isTargetOpcode() &&
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TII->get(N->getTargetOpcode()).getImplicitDefs() &&
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CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs())
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SU->hasPhysRegDefs = true;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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SDNode *OpN = N->getOperand(i).Val;
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if (isPassiveNode(OpN)) continue; // Not scheduled.
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SUnit *OpSU = SUnitMap[OpN].front();
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assert(OpSU && "Node has no SUnit!");
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if (OpSU == SU) continue; // In the same group.
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MVT::ValueType OpVT = N->getOperand(i).getValueType();
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assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
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bool isChain = OpVT == MVT::Other;
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unsigned PhysReg = 0;
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int Cost = 1;
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// Determine if this is a physical register dependency.
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CheckForPhysRegDependency(OpN, N, i, MRI, TII, PhysReg, Cost);
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SU->addPred(OpSU, isChain, false, PhysReg, Cost);
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}
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}
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// Remove MainNode from FlaggedNodes again.
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SU->FlaggedNodes.pop_back();
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}
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return;
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}
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void ScheduleDAG::ComputeLatency(SUnit *SU) {
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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// Compute the latency for the node. We use the sum of the latencies for
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// all nodes flagged together into this SUnit.
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if (InstrItins.isEmpty()) {
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// No latency information.
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SU->Latency = 1;
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} else {
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SU->Latency = 0;
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if (SU->Node->isTargetOpcode()) {
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unsigned SchedClass =
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TII->get(SU->Node->getTargetOpcode()).getSchedClass();
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InstrStage *S = InstrItins.begin(SchedClass);
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InstrStage *E = InstrItins.end(SchedClass);
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for (; S != E; ++S)
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SU->Latency += S->Cycles;
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}
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for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) {
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SDNode *FNode = SU->FlaggedNodes[i];
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if (FNode->isTargetOpcode()) {
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unsigned SchedClass =TII->get(FNode->getTargetOpcode()).getSchedClass();
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InstrStage *S = InstrItins.begin(SchedClass);
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InstrStage *E = InstrItins.end(SchedClass);
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for (; S != E; ++S)
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SU->Latency += S->Cycles;
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}
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}
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}
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}
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void ScheduleDAG::CalculateDepths() {
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std::vector<std::pair<SUnit*, unsigned> > WorkList;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
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if (SUnits[i].Preds.size() == 0)
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WorkList.push_back(std::make_pair(&SUnits[i], 0U));
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while (!WorkList.empty()) {
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SUnit *SU = WorkList.back().first;
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unsigned Depth = WorkList.back().second;
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WorkList.pop_back();
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if (SU->Depth == 0 || Depth > SU->Depth) {
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SU->Depth = Depth;
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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WorkList.push_back(std::make_pair(I->Dep, Depth+1));
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}
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}
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}
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void ScheduleDAG::CalculateHeights() {
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std::vector<std::pair<SUnit*, unsigned> > WorkList;
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SUnit *Root = SUnitMap[DAG.getRoot().Val].front();
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WorkList.push_back(std::make_pair(Root, 0U));
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while (!WorkList.empty()) {
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SUnit *SU = WorkList.back().first;
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unsigned Height = WorkList.back().second;
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WorkList.pop_back();
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if (SU->Height == 0 || Height > SU->Height) {
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SU->Height = Height;
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I)
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WorkList.push_back(std::make_pair(I->Dep, Height+1));
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}
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}
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}
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands (which do
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/// not go into the machine instrs.)
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unsigned ScheduleDAG::CountResults(SDNode *Node) {
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unsigned N = Node->getNumValues();
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while (N && Node->getValueType(N - 1) == MVT::Flag)
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--N;
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if (N && Node->getValueType(N - 1) == MVT::Other)
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--N; // Skip over chain result.
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return N;
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}
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/// CountOperands The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then flag operands. Compute the
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/// number of actual operands that will go into the machine instr.
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unsigned ScheduleDAG::CountOperands(SDNode *Node) {
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
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--N;
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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--N; // Ignore chain if it exists.
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return N;
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}
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static const TargetRegisterClass *getInstrOperandRegClass(
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const MRegisterInfo *MRI,
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const TargetInstrInfo *TII,
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const TargetInstrDesc &II,
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unsigned Op) {
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if (Op >= II.getNumOperands()) {
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assert(II.isVariadic() && "Invalid operand # of instruction");
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return NULL;
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}
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TII->getPointerRegClass();
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return MRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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unsigned InstanceNo, unsigned SrcReg,
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DenseMap<SDOperand, unsigned> &VRBaseMap) {
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unsigned VRBase = 0;
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if (MRegisterInfo::isVirtualRegister(SrcReg)) {
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// Just use the input register directly!
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if (InstanceNo > 0)
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VRBaseMap.erase(SDOperand(Node, ResNo));
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
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assert(isNew && "Node emitted out of order - early");
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return;
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}
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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bool MatchReg = true;
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *Use = *UI;
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bool Match = true;
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if (Use->getOpcode() == ISD::CopyToReg &&
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Use->getOperand(2).Val == Node &&
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Use->getOperand(2).ResNo == ResNo) {
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unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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Match = false;
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} else if (DestReg != SrcReg)
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Match = false;
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} else {
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for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
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SDOperand Op = Use->getOperand(i);
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if (Op.Val != Node || Op.ResNo != ResNo)
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continue;
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MVT::ValueType VT = Node->getValueType(Op.ResNo);
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if (VT != MVT::Other && VT != MVT::Flag)
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Match = false;
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}
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}
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MatchReg &= Match;
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if (VRBase)
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break;
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}
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const TargetRegisterClass *TRC = 0;
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// Figure out the register class to create for the destreg.
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if (VRBase)
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TRC = RegInfo.getRegClass(VRBase);
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else
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TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg);
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// If all uses are reading from the src physical register and copying the
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// register is either impossible or very expensive, then don't create a copy.
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if (MatchReg && TRC->getCopyCost() < 0) {
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VRBase = SrcReg;
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} else {
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// Create the reg, emit the copy.
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VRBase = RegInfo.createVirtualRegister(TRC);
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TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
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}
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if (InstanceNo > 0)
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VRBaseMap.erase(SDOperand(Node, ResNo));
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
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assert(isNew && "Node emitted out of order - early");
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}
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void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
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MachineInstr *MI,
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const TargetInstrDesc &II,
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DenseMap<SDOperand, unsigned> &VRBaseMap) {
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for (unsigned i = 0; i < II.getNumDefs(); ++i) {
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// If the specific node value is only used by a CopyToReg and the dest reg
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// is a vreg, use the CopyToReg'd destination register instead of creating
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// a new vreg.
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unsigned VRBase = 0;
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *Use = *UI;
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if (Use->getOpcode() == ISD::CopyToReg &&
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Use->getOperand(2).Val == Node &&
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Use->getOperand(2).ResNo == i) {
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unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(Reg)) {
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VRBase = Reg;
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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break;
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}
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}
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}
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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if (VRBase == 0) {
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const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
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assert(RC && "Isn't a register operand!");
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VRBase = RegInfo.createVirtualRegister(RC);
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
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assert(isNew && "Node emitted out of order - early");
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}
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}
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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static unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap) {
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DenseMap<SDOperand, unsigned>::iterator I = VRBaseMap.find(Op);
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assert(I != VRBaseMap.end() && "Node emitted out of order - late");
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return I->second;
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}
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDOperand, unsigned> &VRBaseMap) {
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if (Op.isTargetOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Op, VRBaseMap);
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const TargetInstrDesc &TID = MI->getDesc();
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bool isOptDef = (IIOpNum < TID.getNumOperands())
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? (TID.OpInfo[IIOpNum].isOptionalDef()) : false;
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MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II) {
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
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assert(RC && "Don't have operand info for this instruction!");
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const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
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if (VRC != RC) {
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cerr << "Register class of operand and regclass of use don't agree!\n";
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#ifndef NDEBUG
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cerr << "Operand = " << IIOpNum << "\n";
|
|
cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
|
|
cerr << "MI = "; MI->print(cerr);
|
|
cerr << "VReg = " << VReg << "\n";
|
|
cerr << "VReg RegClass size = " << VRC->getSize()
|
|
<< ", align = " << VRC->getAlignment() << "\n";
|
|
cerr << "Expected RegClass size = " << RC->getSize()
|
|
<< ", align = " << RC->getAlignment() << "\n";
|
|
#endif
|
|
cerr << "Fatal error, aborting.\n";
|
|
abort();
|
|
}
|
|
}
|
|
} else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
|
MI->addOperand(MachineOperand::CreateImm(C->getValue()));
|
|
} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
|
|
MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
|
|
} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
|
|
MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
|
|
} else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
|
|
MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
|
|
} else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
|
|
MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
|
|
} else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
|
|
MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
|
|
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
|
|
int Offset = CP->getOffset();
|
|
unsigned Align = CP->getAlignment();
|
|
const Type *Type = CP->getType();
|
|
// MachineConstantPool wants an explicit alignment.
|
|
if (Align == 0) {
|
|
Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
|
|
if (Align == 0) {
|
|
// Alignment of vector types. FIXME!
|
|
Align = TM.getTargetData()->getABITypeSize(Type);
|
|
Align = Log2_64(Align);
|
|
}
|
|
}
|
|
|
|
unsigned Idx;
|
|
if (CP->isMachineConstantPoolEntry())
|
|
Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
|
|
else
|
|
Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
|
|
MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
|
|
} else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
|
|
MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
|
|
} else {
|
|
assert(Op.getValueType() != MVT::Other &&
|
|
Op.getValueType() != MVT::Flag &&
|
|
"Chain and flag operands should occur at end of operand list!");
|
|
unsigned VReg = getVR(Op, VRBaseMap);
|
|
MI->addOperand(MachineOperand::CreateReg(VReg, false));
|
|
|
|
// Verify that it is right.
|
|
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
|
|
if (II) {
|
|
const TargetRegisterClass *RC =
|
|
getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
|
|
assert(RC && "Don't have operand info for this instruction!");
|
|
assert(RegInfo.getRegClass(VReg) == RC &&
|
|
"Register class of operand and regclass of use don't agree!");
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
// Returns the Register Class of a subregister
|
|
static const TargetRegisterClass *getSubRegisterRegClass(
|
|
const TargetRegisterClass *TRC,
|
|
unsigned SubIdx) {
|
|
// Pick the register class of the subregister
|
|
MRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1;
|
|
assert(I < TRC->subregclasses_end() &&
|
|
"Invalid subregister index for register class");
|
|
return *I;
|
|
}
|
|
|
|
static const TargetRegisterClass *getSuperregRegisterClass(
|
|
const TargetRegisterClass *TRC,
|
|
unsigned SubIdx,
|
|
MVT::ValueType VT) {
|
|
// Pick the register class of the superegister for this type
|
|
for (MRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
|
|
E = TRC->superregclasses_end(); I != E; ++I)
|
|
if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
|
|
return *I;
|
|
assert(false && "Couldn't find the register class");
|
|
return 0;
|
|
}
|
|
|
|
/// EmitSubregNode - Generate machine code for subreg nodes.
|
|
///
|
|
void ScheduleDAG::EmitSubregNode(SDNode *Node,
|
|
DenseMap<SDOperand, unsigned> &VRBaseMap) {
|
|
unsigned VRBase = 0;
|
|
unsigned Opc = Node->getTargetOpcode();
|
|
if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
|
|
// If the node is only used by a CopyToReg and the dest reg is a vreg, use
|
|
// the CopyToReg'd destination register instead of creating a new vreg.
|
|
for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
|
|
UI != E; ++UI) {
|
|
SDNode *Use = *UI;
|
|
if (Use->getOpcode() == ISD::CopyToReg &&
|
|
Use->getOperand(2).Val == Node) {
|
|
unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
|
|
if (MRegisterInfo::isVirtualRegister(DestReg)) {
|
|
VRBase = DestReg;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
|
|
|
|
// TODO: If the node is a use of a CopyFromReg from a physical register
|
|
// fold the extract into the copy now
|
|
|
|
// Create the extract_subreg machine instruction.
|
|
MachineInstr *MI =
|
|
new MachineInstr(BB, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
|
|
|
|
// Figure out the register class to create for the destreg.
|
|
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
|
|
const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg);
|
|
const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
|
|
|
|
if (VRBase) {
|
|
// Grab the destination register
|
|
const TargetRegisterClass *DRC = 0;
|
|
DRC = RegInfo.getRegClass(VRBase);
|
|
assert(SRC == DRC &&
|
|
"Source subregister and destination must have the same class");
|
|
} else {
|
|
// Create the reg
|
|
VRBase = RegInfo.createVirtualRegister(SRC);
|
|
}
|
|
|
|
// Add def, source, and subreg index
|
|
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
|
|
AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
|
|
MI->addOperand(MachineOperand::CreateImm(SubIdx));
|
|
|
|
} else if (Opc == TargetInstrInfo::INSERT_SUBREG) {
|
|
assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) &&
|
|
"Malformed insert_subreg node");
|
|
bool isUndefInput = (Node->getNumOperands() == 2);
|
|
unsigned SubReg = 0;
|
|
unsigned SubIdx = 0;
|
|
|
|
if (isUndefInput) {
|
|
SubReg = getVR(Node->getOperand(0), VRBaseMap);
|
|
SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
|
|
} else {
|
|
SubReg = getVR(Node->getOperand(1), VRBaseMap);
|
|
SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
|
|
}
|
|
|
|
// TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
|
|
// to allow coalescing in the allocator
|
|
|
|
// If the node is only used by a CopyToReg and the dest reg is a vreg, use
|
|
// the CopyToReg'd destination register instead of creating a new vreg.
|
|
// If the CopyToReg'd destination register is physical, then fold the
|
|
// insert into the copy
|
|
for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
|
|
UI != E; ++UI) {
|
|
SDNode *Use = *UI;
|
|
if (Use->getOpcode() == ISD::CopyToReg &&
|
|
Use->getOperand(2).Val == Node) {
|
|
unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
|
|
if (MRegisterInfo::isVirtualRegister(DestReg)) {
|
|
VRBase = DestReg;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Create the insert_subreg machine instruction.
|
|
MachineInstr *MI =
|
|
new MachineInstr(BB, TII->get(TargetInstrInfo::INSERT_SUBREG));
|
|
|
|
// Figure out the register class to create for the destreg.
|
|
const TargetRegisterClass *TRC = 0;
|
|
if (VRBase) {
|
|
TRC = RegInfo.getRegClass(VRBase);
|
|
} else {
|
|
TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx,
|
|
Node->getValueType(0));
|
|
assert(TRC && "Couldn't determine register class for insert_subreg");
|
|
VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg
|
|
}
|
|
|
|
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
|
|
AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
|
|
if (!isUndefInput)
|
|
AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap);
|
|
MI->addOperand(MachineOperand::CreateImm(SubIdx));
|
|
} else
|
|
assert(0 && "Node is not a subreg insert or extract");
|
|
|
|
bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
|
|
assert(isNew && "Node emitted out of order - early");
|
|
}
|
|
|
|
/// EmitNode - Generate machine code for an node and needed dependencies.
|
|
///
|
|
void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
|
|
DenseMap<SDOperand, unsigned> &VRBaseMap) {
|
|
// If machine instruction
|
|
if (Node->isTargetOpcode()) {
|
|
unsigned Opc = Node->getTargetOpcode();
|
|
|
|
// Handle subreg insert/extract specially
|
|
if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
|
|
Opc == TargetInstrInfo::INSERT_SUBREG) {
|
|
EmitSubregNode(Node, VRBaseMap);
|
|
return;
|
|
}
|
|
|
|
const TargetInstrDesc &II = TII->get(Opc);
|
|
|
|
unsigned NumResults = CountResults(Node);
|
|
unsigned NodeOperands = CountOperands(Node);
|
|
unsigned NumMIOperands = NodeOperands + NumResults;
|
|
bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
|
|
II.getImplicitDefs() != 0;
|
|
#ifndef NDEBUG
|
|
assert((II.getNumOperands() == NumMIOperands ||
|
|
HasPhysRegOuts || II.isVariadic()) &&
|
|
"#operands for dag node doesn't match .td file!");
|
|
#endif
|
|
|
|
// Create the new machine instruction.
|
|
MachineInstr *MI = new MachineInstr(II);
|
|
|
|
// Add result register values for things that are defined by this
|
|
// instruction.
|
|
if (NumResults)
|
|
CreateVirtualRegisters(Node, MI, II, VRBaseMap);
|
|
|
|
// Emit all of the actual operands of this instruction, adding them to the
|
|
// instruction as appropriate.
|
|
for (unsigned i = 0; i != NodeOperands; ++i)
|
|
AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
|
|
|
|
// Commute node if it has been determined to be profitable.
|
|
if (CommuteSet.count(Node)) {
|
|
MachineInstr *NewMI = TII->commuteInstruction(MI);
|
|
if (NewMI == 0)
|
|
DOUT << "Sched: COMMUTING FAILED!\n";
|
|
else {
|
|
DOUT << "Sched: COMMUTED TO: " << *NewMI;
|
|
if (MI != NewMI) {
|
|
delete MI;
|
|
MI = NewMI;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Now that we have emitted all operands, emit this instruction itself.
|
|
if (!II.usesCustomDAGSchedInsertionHook()) {
|
|
BB->insert(BB->end(), MI);
|
|
} else {
|
|
// Insert this instruction into the end of the basic block, potentially
|
|
// taking some custom action.
|
|
BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
|
|
}
|
|
|
|
// Additional results must be an physical register def.
|
|
if (HasPhysRegOuts) {
|
|
for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
|
|
unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
|
|
if (Node->hasAnyUseOfValue(i))
|
|
EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap);
|
|
}
|
|
}
|
|
} else {
|
|
switch (Node->getOpcode()) {
|
|
default:
|
|
#ifndef NDEBUG
|
|
Node->dump(&DAG);
|
|
#endif
|
|
assert(0 && "This target-independent node should have been selected!");
|
|
case ISD::EntryToken: // fall thru
|
|
case ISD::TokenFactor:
|
|
case ISD::LABEL:
|
|
break;
|
|
case ISD::CopyToReg: {
|
|
unsigned InReg;
|
|
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(2)))
|
|
InReg = R->getReg();
|
|
else
|
|
InReg = getVR(Node->getOperand(2), VRBaseMap);
|
|
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
if (InReg != DestReg) {// Coalesced away the copy?
|
|
const TargetRegisterClass *TRC = 0;
|
|
// Get the target register class
|
|
if (MRegisterInfo::isVirtualRegister(InReg))
|
|
TRC = RegInfo.getRegClass(InReg);
|
|
else
|
|
TRC =
|
|
MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
|
|
InReg);
|
|
TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
|
|
}
|
|
break;
|
|
}
|
|
case ISD::CopyFromReg: {
|
|
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
EmitCopyFromReg(Node, 0, InstanceNo, SrcReg, VRBaseMap);
|
|
break;
|
|
}
|
|
case ISD::INLINEASM: {
|
|
unsigned NumOps = Node->getNumOperands();
|
|
if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
|
|
--NumOps; // Ignore the flag operand.
|
|
|
|
// Create the inline asm machine instruction.
|
|
MachineInstr *MI =
|
|
new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
|
|
|
|
// Add the asm string as an external symbol operand.
|
|
const char *AsmStr =
|
|
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
|
|
MI->addOperand(MachineOperand::CreateES(AsmStr));
|
|
|
|
// Add all of the operand registers to the instruction.
|
|
for (unsigned i = 2; i != NumOps;) {
|
|
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
|
|
unsigned NumVals = Flags >> 3;
|
|
|
|
MI->addOperand(MachineOperand::CreateImm(Flags));
|
|
++i; // Skip the ID value.
|
|
|
|
switch (Flags & 7) {
|
|
default: assert(0 && "Bad flags!");
|
|
case 1: // Use of register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addOperand(MachineOperand::CreateReg(Reg, false));
|
|
}
|
|
break;
|
|
case 2: // Def of register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addOperand(MachineOperand::CreateReg(Reg, true));
|
|
}
|
|
break;
|
|
case 3: { // Immediate.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
if (ConstantSDNode *CS =
|
|
dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
|
|
MI->addOperand(MachineOperand::CreateImm(CS->getValue()));
|
|
} else if (GlobalAddressSDNode *GA =
|
|
dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
|
|
MI->addOperand(MachineOperand::CreateGA(GA->getGlobal(),
|
|
GA->getOffset()));
|
|
} else {
|
|
BasicBlockSDNode *BB =cast<BasicBlockSDNode>(Node->getOperand(i));
|
|
MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 4: // Addressing mode.
|
|
// The addressing mode has been selected, just add all of the
|
|
// operands to the machine instruction.
|
|
for (; NumVals; --NumVals, ++i)
|
|
AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void ScheduleDAG::EmitNoop() {
|
|
TII->insertNoop(*BB, BB->end());
|
|
}
|
|
|
|
void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap) {
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl) continue; // ignore chain preds
|
|
if (!I->Dep->Node) {
|
|
// Copy to physical register.
|
|
DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
|
|
assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
|
|
// Find the destination physical register.
|
|
unsigned Reg = 0;
|
|
for (SUnit::const_succ_iterator II = SU->Succs.begin(),
|
|
EE = SU->Succs.end(); II != EE; ++II) {
|
|
if (I->Reg) {
|
|
Reg = I->Reg;
|
|
break;
|
|
}
|
|
}
|
|
assert(I->Reg && "Unknown physical register!");
|
|
TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
|
|
SU->CopyDstRC, SU->CopySrcRC);
|
|
} else {
|
|
// Copy from physical register.
|
|
assert(I->Reg && "Unknown physical register!");
|
|
unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
|
|
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
|
|
assert(isNew && "Node emitted out of order - early");
|
|
TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
|
|
SU->CopyDstRC, SU->CopySrcRC);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
/// EmitSchedule - Emit the machine code in scheduled order.
|
|
void ScheduleDAG::EmitSchedule() {
|
|
// If this is the first basic block in the function, and if it has live ins
|
|
// that need to be copied into vregs, emit the copies into the top of the
|
|
// block before emitting the code for the block.
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
if (&MF.front() == BB) {
|
|
for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(),
|
|
E = RegInfo.livein_end(); LI != E; ++LI)
|
|
if (LI->second) {
|
|
const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
|
|
TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
|
|
LI->first, RC, RC);
|
|
}
|
|
}
|
|
|
|
|
|
// Finally, emit the code for all of the scheduled instructions.
|
|
DenseMap<SDOperand, unsigned> VRBaseMap;
|
|
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
if (SUnit *SU = Sequence[i]) {
|
|
for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j)
|
|
EmitNode(SU->FlaggedNodes[j], SU->InstanceNo, VRBaseMap);
|
|
if (SU->Node)
|
|
EmitNode(SU->Node, SU->InstanceNo, VRBaseMap);
|
|
else
|
|
EmitCrossRCCopy(SU, CopyVRBaseMap);
|
|
} else {
|
|
// Null SUnit* is a noop.
|
|
EmitNoop();
|
|
}
|
|
}
|
|
}
|
|
|
|
/// dump - dump the schedule.
|
|
void ScheduleDAG::dumpSchedule() const {
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
if (SUnit *SU = Sequence[i])
|
|
SU->dump(&DAG);
|
|
else
|
|
cerr << "**** NOOP ****\n";
|
|
}
|
|
}
|
|
|
|
|
|
/// Run - perform scheduling.
|
|
///
|
|
MachineBasicBlock *ScheduleDAG::Run() {
|
|
Schedule();
|
|
return BB;
|
|
}
|
|
|
|
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
|
|
/// a group of nodes flagged together.
|
|
void SUnit::dump(const SelectionDAG *G) const {
|
|
cerr << "SU(" << NodeNum << "): ";
|
|
if (Node)
|
|
Node->dump(G);
|
|
else
|
|
cerr << "CROSS RC COPY ";
|
|
cerr << "\n";
|
|
if (FlaggedNodes.size() != 0) {
|
|
for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
|
|
cerr << " ";
|
|
FlaggedNodes[i]->dump(G);
|
|
cerr << "\n";
|
|
}
|
|
}
|
|
}
|
|
|
|
void SUnit::dumpAll(const SelectionDAG *G) const {
|
|
dump(G);
|
|
|
|
cerr << " # preds left : " << NumPredsLeft << "\n";
|
|
cerr << " # succs left : " << NumSuccsLeft << "\n";
|
|
cerr << " Latency : " << Latency << "\n";
|
|
cerr << " Depth : " << Depth << "\n";
|
|
cerr << " Height : " << Height << "\n";
|
|
|
|
if (Preds.size() != 0) {
|
|
cerr << " Predecessors:\n";
|
|
for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl)
|
|
cerr << " ch #";
|
|
else
|
|
cerr << " val #";
|
|
cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
|
|
if (I->isSpecial)
|
|
cerr << " *";
|
|
cerr << "\n";
|
|
}
|
|
}
|
|
if (Succs.size() != 0) {
|
|
cerr << " Successors:\n";
|
|
for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
|
|
I != E; ++I) {
|
|
if (I->isCtrl)
|
|
cerr << " ch #";
|
|
else
|
|
cerr << " val #";
|
|
cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
|
|
if (I->isSpecial)
|
|
cerr << " *";
|
|
cerr << "\n";
|
|
}
|
|
}
|
|
cerr << "\n";
|
|
}
|