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GlobalISel
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intrinsics
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rvv
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[LegalizeTypes][VP] Add widening support for binary VP ops
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2021-08-19 13:08:47 +01:00 |
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add-before-shl.ll
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[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
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2021-08-18 10:22:00 -07:00 |
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add-imm.ll
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[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
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2021-08-18 11:07:11 -07:00 |
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addc-adde-sube-subc.ll
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…
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addcarry.ll
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…
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addimm-mulimm.ll
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[RISCV][test] Improve tests for (add (mul x, c1), c2)
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2021-08-19 21:04:35 +08:00 |
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addrspacecast.ll
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[RISCV] Assume no-op addrspacecasts by default
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2020-12-18 21:03:37 +00:00 |
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aext-to-sext.ll
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[RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being called for an illegal i32 shift amount.
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2021-06-29 09:45:13 -07:00 |
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align-loops.ll
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[CodeGen] Add -align-loops
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2021-08-04 12:45:18 -07:00 |
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align.ll
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…
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alloca.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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alu8.ll
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Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions."
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2021-06-27 10:33:43 -07:00 |
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alu16.ll
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[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
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2021-04-11 13:59:51 -07:00 |
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alu32.ll
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[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
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2021-08-18 10:44:25 -07:00 |
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alu64.ll
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[RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.
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2020-11-25 21:57:48 -08:00 |
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analyze-branch.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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arith-with-overflow.ll
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…
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atomic-cmpxchg-flag.ll
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…
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atomic-cmpxchg.ll
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[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
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2021-08-18 10:22:00 -07:00 |
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atomic-fence.ll
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…
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atomic-load-store.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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atomic-rmw.ll
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[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
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2021-08-18 10:22:00 -07:00 |
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atomic-signext.ll
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[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
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2021-08-18 10:22:00 -07:00 |
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attributes.ll
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[RISCV] Update the version number to v0.10 for vector.
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2021-01-30 07:20:05 +08:00 |
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blockaddress.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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branch-relaxation.ll
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[RISCV] Indirect branch generation in position independent code
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2020-08-17 13:09:26 +01:00 |
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branch.ll
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[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
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2021-03-15 11:32:43 -07:00 |
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bswap-ctlz-cttz-ctpop.ll
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Revert "Allow rematerialization of virtual reg uses"
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2021-08-18 00:12:41 -07:00 |
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byval.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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callee-saved-fpr32s.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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callee-saved-fpr64s.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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callee-saved-gprs.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-half.ll
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[RISCV] Improve constant materialization for stores of i16 or i32 negative constants.
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2021-08-18 10:25:12 -07:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32d.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32f-ilp32d-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-lp64-lp64f-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-lp64-lp64f-lp64d-common.ll
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[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
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2021-08-18 10:22:00 -07:00 |
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calling-conv-lp64.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-rv32f-ilp32.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-sext-zext.ll
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[RISCV] Don't print zext.b alias.
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2021-01-05 10:41:08 -08:00 |
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calling-conv-vector-float.ll
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[RISCV] Fix a crash when lowering split float arguments
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2021-07-22 09:55:26 +01:00 |
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calls.ll
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[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
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2021-07-13 09:46:21 -07:00 |
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cmp-bool.ll
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[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
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2020-07-15 07:34:22 +00:00 |
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codemodel-lowering.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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compress-float.ll
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…
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compress-inline-asm.ll
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…
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compress.ll
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[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
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2020-12-04 10:34:12 -08:00 |
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copy-frameindex.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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copysign-casts.ll
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Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions."
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2021-06-27 10:33:43 -07:00 |
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disable-tail-calls.ll
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disjoint.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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div.ll
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[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
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2021-08-18 10:22:00 -07:00 |
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double-arith.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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double-bitmanip-dagcombines.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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double-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
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2021-01-19 11:21:48 -08:00 |
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double-calling-conv.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-convert.ll
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[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
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2021-08-07 16:06:00 -07:00 |
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double-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
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2021-01-12 10:45:03 -08:00 |
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double-frem.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-imm.ll
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…
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double-intrinsics.ll
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[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
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2021-07-06 11:43:22 -07:00 |
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double-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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double-mem.ll
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[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
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2021-07-20 09:22:06 -07:00 |
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double-previous-failure.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
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2021-01-14 13:41:40 -08:00 |
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double-stack-spill-restore.ll
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[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
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2021-08-18 10:44:25 -07:00 |
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dwarf-eh.ll
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…
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elf-preemption.ll
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[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
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2021-05-11 11:29:45 -07:00 |
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exception-pointer-register.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fastcc-float.ll
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[RISCV] Fix a crash when lowering split float arguments
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2021-07-22 09:55:26 +01:00 |
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fastcc-int.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fixups-diff.ll
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test: clean up some of the RISCV tests (NFC)
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2021-06-17 09:51:09 -07:00 |
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fixups-relax-diff.ll
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test: clean up some of the RISCV tests (NFC)
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2021-06-17 09:51:09 -07:00 |
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float-arith.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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float-bit-preserving-dagcombines.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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float-bitmanip-dagcombines.ll
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…
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float-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
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2021-01-19 11:21:48 -08:00 |
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float-convert.ll
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[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
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2021-08-07 16:06:00 -07:00 |
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float-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
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2021-01-12 10:45:03 -08:00 |
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float-frem.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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float-imm.ll
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…
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float-intrinsics.ll
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[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
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2021-07-06 11:43:22 -07:00 |
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float-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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float-mem.ll
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[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
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2021-07-20 09:22:06 -07:00 |
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float-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
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2021-01-14 13:41:40 -08:00 |
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flt-rounds.ll
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…
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fold-addi-loadstore.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
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2020-12-30 15:28:11 -08:00 |
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fp-imm.ll
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…
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fp16-promote.ll
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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
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2021-04-01 12:41:57 -07:00 |
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fp128.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fpenv.ll
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[RISCV] Custom lowering of SET_ROUNDING
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2021-04-22 15:04:55 +07:00 |
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frame-info.ll
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[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
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2021-01-15 11:14:14 -08:00 |
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frame.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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frameaddr-returnaddr.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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get-register-invalid.ll
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…
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get-register-noreserve.ll
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…
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get-register-reserve.ll
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…
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get-setcc-result-type.ll
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…
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ghccc-rv32.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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ghccc-rv64.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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half-arith.ll
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[RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first.
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2020-12-02 21:13:42 -08:00 |
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half-bitmanip-dagcombines.ll
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[RISCV] Add optimizations for FMV_X_ANYEXTH similar to FMV_X_ANYEXTW_RV64.
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2021-08-08 18:30:48 -07:00 |
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half-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
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2021-01-19 11:21:48 -08:00 |
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half-convert.ll
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[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
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2021-08-07 16:06:00 -07:00 |
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half-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
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2021-01-12 10:45:03 -08:00 |
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half-imm.ll
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[RISCV] Support Zfh half-precision floating-point extension.
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2020-12-03 09:16:33 +08:00 |
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half-intrinsics.ll
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[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
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2021-07-06 11:43:22 -07:00 |
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half-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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half-mem.ll
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[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
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2021-07-20 09:22:06 -07:00 |
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half-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
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2021-01-14 13:41:40 -08:00 |
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hoist-global-addr-base.ll
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[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
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2021-03-15 11:32:43 -07:00 |
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i32-icmp.ll
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…
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imm-cse.ll
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…
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imm.ll
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[RISCV] Improve constant materialization for stores of i16 or i32 negative constants.
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2021-08-18 10:25:12 -07:00 |
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indirectbr.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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init-array.ll
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…
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inline-asm-S-constraint.ll
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[RISCV] Support machine constraint "S"
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2021-07-13 09:30:09 -07:00 |
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inline-asm-abi-names.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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inline-asm-clobbers.ll
|
…
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inline-asm-d-abi-names.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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inline-asm-d-constraint-f.ll
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…
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inline-asm-f-abi-names.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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inline-asm-f-constraint-f.ll
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…
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inline-asm-i-constraint-i1.ll
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…
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inline-asm-invalid.ll
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…
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inline-asm.ll
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[MC][RISCV] Set UseIntegratedAssembler to true
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2020-07-12 21:04:48 -07:00 |
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interrupt-attr-args-error.ll
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…
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interrupt-attr-callee.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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interrupt-attr-invalid.ll
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…
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interrupt-attr-nocall.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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interrupt-attr-ret-error.ll
|
…
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interrupt-attr.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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jumptable.ll
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[CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt.
|
2021-06-23 15:38:11 -07:00 |
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large-stack.ll
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[RISCV] remove redundant instruction when eliminate frame index
|
2021-03-21 18:54:00 +08:00 |
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legalize-fneg.ll
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…
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lit.local.cfg
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…
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lsr-legaladdimm.ll
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…
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machineoutliner.mir
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…
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mattr-invalid-combination.ll
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…
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mem.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
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mem64.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
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mir-target-flags.ll
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[TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm
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2020-12-05 14:54:37 -08:00 |
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module-target-abi.ll
|
…
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module-target-abi2.ll
|
…
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mul.ll
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[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
|
2021-08-18 10:44:25 -07:00 |
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musttail-call.ll
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OpaquePtr: Bulk update tests to use typed sret
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2020-11-20 17:58:26 -05:00 |
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neg-abs.ll
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[RISCV][NFC] Increase test coverage of Zbt extension
|
2021-01-18 17:30:35 +00:00 |
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nomerge.ll
|
…
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option-nopic.ll
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…
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option-norelax.ll
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…
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option-norvc.ll
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…
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option-pic.ll
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…
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option-relax.ll
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…
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option-rvc.ll
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…
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out-of-reach-emergency-slot.mir
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[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer
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2021-01-23 09:10:03 +00:00 |
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patchable-function-entry.ll
|
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"
|
2021-05-29 15:11:37 +01:00 |
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pic-models.ll
|
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
|
2020-07-14 11:15:01 +01:00 |
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pr40333.ll
|
…
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pr51206.ll
|
[RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop.
|
2021-07-28 09:05:45 -07:00 |
|
prefetch.ll
|
…
|
|
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readcyclecounter.ll
|
…
|
|
|
rem.ll
|
[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)
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2021-07-20 08:53:55 -07:00 |
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remat.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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reserved-reg-errors.ll
|
…
|
|
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reserved-regs.ll
|
…
|
|
|
rotl-rotr.ll
|
…
|
|
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rv32e.ll
|
…
|
|
|
rv32i-rv64i-float-double.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv32i-rv64i-half.ll
|
Revert "Allow rematerialization of virtual reg uses"
|
2021-08-18 00:12:41 -07:00 |
|
rv32zba.ll
|
[RISCV][test] Add new tests for add optimization in the zba extension
|
2021-08-19 19:59:23 +08:00 |
|
rv32zbb-intrinsic.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv32zbb-zbp.ll
|
Revert "Allow rematerialization of virtual reg uses"
|
2021-08-18 00:12:41 -07:00 |
|
rv32zbb.ll
|
Revert "Allow rematerialization of virtual reg uses"
|
2021-08-18 00:12:41 -07:00 |
|
rv32zbc-intrinsic.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv32zbe-intrinsic.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv32zbp-intrinsic.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv32zbp.ll
|
Revert "Allow rematerialization of virtual reg uses"
|
2021-08-18 00:12:41 -07:00 |
|
rv32zbr.ll
|
[RISCV] Add IR intrinsic for Zbr extension
|
2021-04-02 10:58:45 -07:00 |
|
rv32zbs.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv32zbt.ll
|
Revert "Allow rematerialization of virtual reg uses"
|
2021-08-18 00:12:41 -07:00 |
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rv64-large-stack.ll
|
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
|
2021-07-20 09:22:06 -07:00 |
|
rv64d-double-convert.ll
|
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
|
2021-07-24 10:50:43 -07:00 |
|
rv64f-float-convert.ll
|
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
|
2021-07-24 10:50:43 -07:00 |
|
rv64f-half-convert.ll
|
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
|
2021-07-24 10:50:43 -07:00 |
|
rv64i-complex-float.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv64i-demanded-bits.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64i-double-softfloat.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv64i-exhaustive-w-insts.ll
|
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
|
2021-08-18 10:44:25 -07:00 |
|
rv64i-single-softfloat.ll
|
Update @llvm.powi to handle different int sizes for the exponent
|
2021-06-17 09:38:28 +02:00 |
|
rv64i-tricky-shifts.ll
|
…
|
|
|
rv64i-w-insts-legalization.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64m-exhaustive-w-insts.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64m-w-insts-legalization.ll
|
Revert "[BPI] Improve static heuristics for integer comparisons"
|
2020-08-17 20:44:33 +02:00 |
|
rv64zba.ll
|
[RISCV][test] Add new tests for add optimization in the zba extension
|
2021-08-19 19:59:23 +08:00 |
|
rv64zbb-intrinsic.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv64zbb-zbp.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64zbb.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64zbc-intrinsic.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv64zbe-intrinsic.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv64zbp-intrinsic.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv64zbp.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv64zbr.ll
|
[RISCV] Add IR intrinsic for Zbr extension
|
2021-04-02 10:58:45 -07:00 |
|
rv64zbs.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
rv64zbt.ll
|
[RISCV] Improve check prefixes in B extension tests. NFC
|
2021-08-12 12:41:40 -07:00 |
|
sadd_sat.ll
|
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
|
2021-04-07 13:47:17 -07:00 |
|
sadd_sat_plus.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
saverestore.ll
|
[RISCV] Don't emit save-restore call if function is a interrupt handler
|
2021-04-16 12:54:47 +08:00 |
|
scalable-vector-struct.ll
|
[RISCV] Use whole register load/store for generic load/store.
|
2021-02-09 15:52:04 +08:00 |
|
sdata-limit-0.ll
|
…
|
|
|
sdata-limit-4.ll
|
…
|
|
|
sdata-limit-8.ll
|
…
|
|
|
sdata-local-sym.ll
|
…
|
|
|
select-and.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-bare.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-binop-identity.ll
|
[RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y))
|
2021-08-10 09:02:56 -07:00 |
|
select-cc.ll
|
[RISCV] Support RISCVISD::SELECT_CC in ComputeNumSignBitsForTargetNode.
|
2021-08-13 18:00:09 -07:00 |
|
select-const.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-optimize-multiple.ll
|
[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
|
2021-01-22 14:51:22 -08:00 |
|
select-optimize-multiple.mir
|
[RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC
|
2021-08-08 17:25:37 -07:00 |
|
select-or.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
setcc-logic.ll
|
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
|
2021-08-18 10:44:25 -07:00 |
|
sext-zext-trunc.ll
|
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
|
2021-01-25 16:37:21 -08:00 |
|
shadowcallstack.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
shift-masked-shamt.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
shifts.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
shrinkwrap.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
spill-fpr-scalar.ll
|
[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.
|
2021-07-23 09:12:05 -07:00 |
|
split-offsets.ll
|
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
|
2021-08-18 10:44:25 -07:00 |
|
split-sp-adjust.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
srem-lkk.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
srem-seteq-illegal-types.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
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srem-vector-lkk.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
ssub_sat.ll
|
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
|
2021-04-07 13:47:17 -07:00 |
|
ssub_sat_plus.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
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2021-08-18 10:22:00 -07:00 |
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stack-realignment-with-variable-sized-objects.ll
|
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
|
2021-01-15 11:14:14 -08:00 |
|
stack-realignment.ll
|
[RISCV] remove redundant instruction when eliminate frame index
|
2021-03-21 18:54:00 +08:00 |
|
stack-slot-size.ll
|
[RISCV] Fix stack slot for argument types (Bug 49500)
|
2021-04-29 09:10:48 +01:00 |
|
stack-store-check.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
subtarget-features-std-ext.ll
|
…
|
|
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tail-calls.ll
|
[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
|
2021-07-13 09:46:21 -07:00 |
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target-abi-invalid.ll
|
…
|
|
|
target-abi-valid.ll
|
…
|
|
|
thread-pointer.ll
|
…
|
|
|
tls-models.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
uadd_sat.ll
|
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
|
2021-03-16 07:44:06 -07:00 |
|
uadd_sat_plus.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
umulo-128-legalisation-lowering.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
urem-lkk.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
urem-seteq-illegal-types.ll
|
[RISCV] Select vector shl by 1 to a vector add.
|
2021-07-27 10:57:28 -07:00 |
|
urem-vector-lkk.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
usub_sat.ll
|
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
|
2021-03-16 07:44:06 -07:00 |
|
usub_sat_plus.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
vararg.ll
|
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
|
2021-08-18 10:44:25 -07:00 |
|
vec3-setcc-crash.ll
|
Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions."
|
2021-06-27 10:33:43 -07:00 |
|
vector-abi.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
verify-instr.mir
|
…
|
|
|
wide-mem.ll
|
[RISCV] Fold ADDIs into load/stores with nonzero offsets
|
2020-07-06 17:32:57 +01:00 |
|
xaluo.ll
|
[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
|
2021-08-18 11:07:11 -07:00 |
|
zext-with-load-is-free.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
zfh-imm.ll
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
b10e74389e