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llvm-project/llvm/test/CodeGen/MIR
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Wang, Pengfei 6f7f5b54c8 [X86] AVX512FP16 instructions enabling 1/6 
1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105263
 		2021-08-10 12:46:01 +08:00
..
AArch64 CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
AMDGPU CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ARM CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Generic [MIRParser] Add machine metadata. 2021-06-28 22:29:36 -04:00
Hexagon CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Mips CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
NVPTX
…
PowerPC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
WebAssembly
…
X86 [X86] AVX512FP16 instructions enabling 1/6 2021-08-10 12:46:01 +08:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.