forked from OSchip/llvm-project
330 lines
12 KiB
YAML
330 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_min_max_ValK0_K1_u32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_min_max_ValK0_K1_u32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_UMED3 [[COPY]], [[C]], [[C1]]
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; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 12
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_UMAX %0, %7
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%4:sgpr(s32) = G_CONSTANT i32 17
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_UMIN %3, %8
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: min_max_ValK0_K1_i32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: min_max_ValK0_K1_i32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_UMED3 [[COPY]], [[C]], [[C1]]
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; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 12
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_UMAX %7, %0
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%4:sgpr(s32) = G_CONSTANT i32 17
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_UMIN %3, %8
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_min_K1max_ValK0__u32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_min_K1max_ValK0__u32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_UMED3 [[COPY]], [[C]], [[C1]]
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; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 12
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_UMAX %0, %7
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%4:sgpr(s32) = G_CONSTANT i32 17
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_UMIN %8, %3
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_min_K1max_K0Val__u32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_min_K1max_K0Val__u32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_UMED3 [[COPY]], [[C]], [[C1]]
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; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 12
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_UMAX %7, %0
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%4:sgpr(s32) = G_CONSTANT i32 17
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_UMIN %8, %3
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_min_ValK1_K0_u32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_min_ValK1_K0_u32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_UMED3 [[COPY]], [[C1]], [[C]]
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; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 17
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_UMIN %0, %7
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%4:sgpr(s32) = G_CONSTANT i32 12
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_UMAX %3, %8
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_min_K1Val_K0_u32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_min_K1Val_K0_u32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_UMED3 [[COPY]], [[C1]], [[C]]
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; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 17
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_UMIN %7, %0
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%4:sgpr(s32) = G_CONSTANT i32 12
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_UMAX %3, %8
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_K0min_ValK1__u32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_K0min_ValK1__u32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_UMED3 [[COPY]], [[C1]], [[C]]
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; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 17
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_UMIN %0, %7
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%4:sgpr(s32) = G_CONSTANT i32 12
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_UMAX %8, %3
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_K0min_K1Val__u32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_K0min_K1Val__u32
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_UMED3 [[COPY]], [[C1]], [[C]]
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; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%2:sgpr(s32) = G_CONSTANT i32 17
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%7:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_UMIN %7, %0
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%4:sgpr(s32) = G_CONSTANT i32 12
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%8:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = G_UMAX %8, %3
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$vgpr0 = COPY %5(s32)
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%6:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %6, implicit $vgpr0
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...
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---
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name: test_max_K0min_K1Val__v2u16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK-LABEL: name: test_max_K0min_K1Val__v2u16
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; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
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; CHECK: [[UMIN:%[0-9]+]]:vgpr(<2 x s16>) = G_UMIN [[COPY2]], [[COPY]]
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
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; CHECK: [[UMAX:%[0-9]+]]:vgpr(<2 x s16>) = G_UMAX [[COPY3]], [[UMIN]]
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; CHECK: $vgpr0 = COPY [[UMAX]](<2 x s16>)
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; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
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; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:sgpr_64 = COPY $sgpr30_sgpr31
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%9:sgpr(s32) = G_CONSTANT i32 17
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %9(s32), %9(s32)
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%10:sgpr(s32) = G_CONSTANT i32 12
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%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %10(s32), %10(s32)
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%11:vgpr(<2 x s16>) = COPY %2(<2 x s16>)
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%4:vgpr(<2 x s16>) = G_UMIN %11, %0
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%12:vgpr(<2 x s16>) = COPY %5(<2 x s16>)
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%7:vgpr(<2 x s16>) = G_UMAX %12, %4
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$vgpr0 = COPY %7(<2 x s16>)
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%8:ccr_sgpr_64 = COPY %1
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S_SETPC_B64_return %8, implicit $vgpr0
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...
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---
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name: test_uniform_min_max
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $sgpr2
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; CHECK-LABEL: name: test_uniform_min_max
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; CHECK: liveins: $sgpr2
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
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; CHECK: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[COPY]], [[C]]
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17
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; CHECK: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[UMAX]], [[C1]]
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UMIN]](s32)
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; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
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; CHECK: $sgpr0 = COPY [[INT]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%0:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_CONSTANT i32 12
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%4:sgpr(s32) = G_UMAX %0, %3
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%5:sgpr(s32) = G_CONSTANT i32 17
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%6:sgpr(s32) = G_UMIN %4, %5
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%8:vgpr(s32) = COPY %6(s32)
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%7:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %8(s32)
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$sgpr0 = COPY %7(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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