forked from OSchip/llvm-project
61 lines
1.7 KiB
ArmAsm
61 lines
1.7 KiB
ArmAsm
# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \
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# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \
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# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
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# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
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# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d - \
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# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
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# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d -M no-aliases - \
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# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
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# Tests compressed instructions available in rv64 and not in rv32.
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# CHECK-BYTES: e0 7f
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# CHECK-ALIAS: ld s0, 248(a5)
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# CHECK-INST: c.ld s0, 248(a5)
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# CHECK: # encoding: [0xe0,0x7f]
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ld s0, 248(a5)
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# CHECK-BYTES: a0 e3
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# CHECK-ALIAS: sd s0, 64(a5)
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# CHECK-INST: c.sd s0, 64(a5)
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# CHECK: # encoding: [0xa0,0xe3]
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sd s0, 64(a5)
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# CHECK-BYTES: 7d 22
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# CHEACK-ALIAS: addiw tp, tp, 31
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# CHECK-INST: c.addiw tp, 31
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# CHECK: # encoding: [0x7d,0x22]
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addiw tp, tp, 31
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# CHECK-BYTES: 1d 9c
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# CHEACK-ALIAS: subw s0, s0, a5
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# CHECK-INST: c.subw s0, a5
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# CHECK: # encoding: [0x1d,0x9c]
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subw s0, s0, a5
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# CHECK-BYTES: 3d 9c
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# CHECK-ALIAS: addw s0, s0, a5
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# CHECK-INST: c.addw s0, a5
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# CHECK: # encoding: [0x3d,0x9c]
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addw s0, s0, a5
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# CHECK-BYTES: 3d 9c
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# CHECK-ALIAS: addw s0, s0, a5
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# CHECK-INST: c.addw s0, a5
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# CHECK: # encoding: [0x3d,0x9c]
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addw s0, a5, s0
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# CHECK-BYTES: ee 70
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# CHECK-ALIAS: ld ra, 248(sp)
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# CHECK-INST: c.ldsp ra, 248(sp)
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# CHECK: # encoding: [0xee,0x70]
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ld ra, 248(sp)
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# CHECK-BYTES: a2 e0
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# CHECK-ALIAS: sd s0, 64(sp)
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# CHECK-INST: c.sdsp s0, 64(sp)
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# CHECK: # encoding: [0xa2,0xe0]
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sd s0, 64(sp)
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