Hsiangkai Wang aa8d33a6d6 [RISCV] Spilling for Zvlsseg registers. ... For Zvlsseg, we create several tuple register classes. When spilling for these tuple register classes, we need to iterate NF times to load/store these tuple registers. Differential Revision: https://reviews.llvm.org/D98629		2021-03-19 07:46:16 +08:00
..
AArch64	Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"	2021-03-18 16:01:02 -07:00
AMDGPU	[AMDGPU] Remove cpol, tfe, and swz from MUBUF patterns	2021-03-18 14:36:04 -07:00
ARC	…
ARM	[ARM] Regenerate select-imm.ll tests	2021-03-18 11:07:16 +00:00
AVR	…
BPF	…
Generic	[XCore] Remove XFAIL: xcore from passing test.	2021-03-18 15:46:24 +00:00
Hexagon	[Hexagon] Add support for named registers cs0 and cs1	2021-03-18 09:53:22 -05:00
Inputs	…
Lanai	…
M68k	[M68k] Fixed incorrect `extract-section` command substitution	2021-03-16 13:37:50 -07:00
MIR	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
MSP430	…
Mips	Test cases for rem-seteq fold with illegal types	2021-03-12 16:28:04 +02:00
NVPTX	[NVPTX] CUDA does provide malloc/free since compute capability 2.X	2021-03-15 22:45:56 -05:00
PowerPC	[NFC] [XCOFF] Update PowerPC readobj test case with expression	2021-03-17 16:02:50 +08:00
RISCV	[RISCV] Spilling for Zvlsseg registers.	2021-03-19 07:46:16 +08:00
SPARC	…
SystemZ	…
Thumb	[ARM] Use lrdsb for more thumb1 loads.	2021-03-17 15:29:02 +00:00
Thumb2	Test cases for rem-seteq fold with illegal types	2021-03-12 16:28:04 +02:00
VE	…
WebAssembly	[WebAssembly] Finalize SIMD names and opcodes	2021-03-18 11:21:25 -07:00
WinCFGuard	…
WinEH	…
X86	[DAG] Improve folding (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x)	2021-03-18 15:34:53 +00:00
XCore	…