..
AArch64
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
AMDGPU
[AMDGPU] Remove cpol, tfe, and swz from MUBUF patterns
2021-03-18 14:36:04 -07:00
ARC
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ARM
[ARM] Regenerate select-imm.ll tests
2021-03-18 11:07:16 +00:00
AVR
[AVR] Fix lifeness issues in the AVR backend
2021-03-04 14:04:39 +01:00
BPF
[BPF] Add support for floats and doubles
2021-03-05 15:10:11 +01:00
Generic
[XCore] Remove XFAIL: xcore from passing test.
2021-03-18 15:46:24 +00:00
Hexagon
[Hexagon] Add support for named registers cs0 and cs1
2021-03-18 09:53:22 -05:00
Inputs
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Lanai
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M68k
[M68k] Fixed incorrect `extract-section` command substitution
2021-03-16 13:37:50 -07:00
MIR
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
MSP430
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Mips
Test cases for rem-seteq fold with illegal types
2021-03-12 16:28:04 +02:00
NVPTX
[NVPTX] CUDA does provide malloc/free since compute capability 2.X
2021-03-15 22:45:56 -05:00
PowerPC
[NFC] [XCOFF] Update PowerPC readobj test case with expression
2021-03-17 16:02:50 +08:00
RISCV
[RISCV] Spilling for Zvlsseg registers.
2021-03-19 07:46:16 +08:00
SPARC
[LegalizeTypes] Improve ExpandIntRes_XMULO codegen.
2021-03-01 09:54:32 -08:00
SystemZ
[SystemZ] Reimplement the i8/i16 compare-and-swap logic.
2021-03-03 14:04:32 -06:00
Thumb
[ARM] Use lrdsb for more thumb1 loads.
2021-03-17 15:29:02 +00:00
Thumb2
Test cases for rem-seteq fold with illegal types
2021-03-12 16:28:04 +02:00
VE
[test] Fix CodeGen/VE/Scalar tests
2021-03-02 15:30:44 -08:00
WebAssembly
[WebAssembly] Finalize SIMD names and opcodes
2021-03-18 11:21:25 -07:00
WinCFGuard
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WinEH
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X86
[DAG] Improve folding (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x)
2021-03-18 15:34:53 +00:00
XCore
[CodeGen] Report a normal instead of fatal error for label redefinition
2021-03-09 10:54:41 +00:00
aa8d33a6d6