forked from OSchip/llvm-project
242 lines
7.3 KiB
C++
242 lines
7.3 KiB
C++
//===--- Sparc.h - declare sparc target feature support ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares Sparc TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_SPARC_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_SPARC_H
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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namespace clang {
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namespace targets {
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// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
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class LLVM_LIBRARY_VISIBILITY SparcTargetInfo : public TargetInfo {
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static const TargetInfo::GCCRegAlias GCCRegAliases[];
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static const char *const GCCRegNames[];
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bool SoftFloat;
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public:
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SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
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: TargetInfo(Triple), SoftFloat(false) {}
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int getEHDataRegisterNumber(unsigned RegNo) const override {
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if (RegNo == 0)
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return 24;
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if (RegNo == 1)
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return 25;
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return -1;
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}
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bool handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) override {
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// Check if software floating point is enabled
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auto Feature = llvm::find(Features, "+soft-float");
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if (Feature != Features.end()) {
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SoftFloat = true;
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}
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return true;
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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bool hasFeature(StringRef Feature) const override;
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bool hasSjLjLowering() const override { return true; }
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ArrayRef<Builtin::Info> getTargetBuiltins() const override {
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// FIXME: Implement!
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return None;
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}
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BuiltinVaListKind getBuiltinVaListKind() const override {
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return TargetInfo::VoidPtrBuiltinVaList;
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}
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ArrayRef<const char *> getGCCRegNames() const override;
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ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &info) const override {
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// FIXME: Implement!
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switch (*Name) {
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case 'I': // Signed 13-bit constant
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case 'J': // Zero
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case 'K': // 32-bit constant with the low 12 bits clear
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case 'L': // A constant in the range supported by movcc (11-bit signed imm)
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case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
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case 'N': // Same as 'K' but zext (required for SIMode)
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case 'O': // The constant 4096
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return true;
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case 'f':
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case 'e':
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info.setAllowsRegister();
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return true;
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}
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return false;
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}
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const char *getClobbers() const override {
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// FIXME: Implement!
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return "";
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}
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// No Sparc V7 for now, the backend doesn't support it anyway.
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enum CPUKind {
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CK_GENERIC,
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CK_V8,
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CK_SUPERSPARC,
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CK_SPARCLITE,
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CK_F934,
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CK_HYPERSPARC,
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CK_SPARCLITE86X,
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CK_SPARCLET,
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CK_TSC701,
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CK_V9,
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CK_ULTRASPARC,
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CK_ULTRASPARC3,
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CK_NIAGARA,
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CK_NIAGARA2,
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CK_NIAGARA3,
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CK_NIAGARA4,
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CK_MYRIAD2100,
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CK_MYRIAD2150,
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CK_MYRIAD2155,
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CK_MYRIAD2450,
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CK_MYRIAD2455,
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CK_MYRIAD2x5x,
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CK_MYRIAD2080,
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CK_MYRIAD2085,
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CK_MYRIAD2480,
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CK_MYRIAD2485,
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CK_MYRIAD2x8x,
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CK_LEON2,
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CK_LEON2_AT697E,
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CK_LEON2_AT697F,
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CK_LEON3,
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CK_LEON3_UT699,
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CK_LEON3_GR712RC,
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CK_LEON4,
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CK_LEON4_GR740
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} CPU = CK_GENERIC;
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enum CPUGeneration {
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CG_V8,
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CG_V9,
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};
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CPUGeneration getCPUGeneration(CPUKind Kind) const;
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CPUKind getCPUKind(StringRef Name) const;
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bool isValidCPUName(StringRef Name) const override {
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return getCPUKind(Name) != CK_GENERIC;
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}
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool setCPU(const std::string &Name) override {
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CPU = getCPUKind(Name);
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return CPU != CK_GENERIC;
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}
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};
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// SPARC v8 is the 32-bit mode selected by Triple::sparc.
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class LLVM_LIBRARY_VISIBILITY SparcV8TargetInfo : public SparcTargetInfo {
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public:
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SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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: SparcTargetInfo(Triple, Opts) {
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resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64");
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// NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
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switch (getTriple().getOS()) {
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default:
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SizeType = UnsignedInt;
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IntPtrType = SignedInt;
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PtrDiffType = SignedInt;
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break;
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case llvm::Triple::NetBSD:
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case llvm::Triple::OpenBSD:
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SizeType = UnsignedLong;
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IntPtrType = SignedLong;
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PtrDiffType = SignedLong;
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break;
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}
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// Up to 32 bits (V8) or 64 bits (V9) are lock-free atomic, but we're
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// willing to do atomic ops on up to 64 bits.
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MaxAtomicPromoteWidth = 64;
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if (getCPUGeneration(CPU) == CG_V9)
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MaxAtomicInlineWidth = 64;
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else
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// FIXME: This isn't correct for plain V8 which lacks CAS,
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// only for LEON 3+ and Myriad.
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MaxAtomicInlineWidth = 32;
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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bool hasSjLjLowering() const override { return true; }
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bool hasExtIntType() const override { return true; }
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};
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// SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
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class LLVM_LIBRARY_VISIBILITY SparcV8elTargetInfo : public SparcV8TargetInfo {
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public:
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SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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: SparcV8TargetInfo(Triple, Opts) {
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resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64");
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}
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};
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// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
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class LLVM_LIBRARY_VISIBILITY SparcV9TargetInfo : public SparcTargetInfo {
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public:
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SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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: SparcTargetInfo(Triple, Opts) {
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// FIXME: Support Sparc quad-precision long double?
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resetDataLayout("E-m:e-i64:64-n32:64-S128");
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// This is an LP64 platform.
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LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
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// OpenBSD uses long long for int64_t and intmax_t.
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if (getTriple().isOSOpenBSD())
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IntMaxType = SignedLongLong;
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else
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IntMaxType = SignedLong;
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Int64Type = IntMaxType;
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// The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
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// aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
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LongDoubleWidth = 128;
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LongDoubleAlign = 128;
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SuitableAlign = 128;
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LongDoubleFormat = &llvm::APFloat::IEEEquad();
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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bool isValidCPUName(StringRef Name) const override {
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return getCPUGeneration(SparcTargetInfo::getCPUKind(Name)) == CG_V9;
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}
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool setCPU(const std::string &Name) override {
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if (!SparcTargetInfo::setCPU(Name))
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return false;
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return getCPUGeneration(CPU) == CG_V9;
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}
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bool hasExtIntType() const override { return true; }
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};
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} // namespace targets
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} // namespace clang
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#endif // LLVM_CLANG_LIB_BASIC_TARGETS_SPARC_H
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