llvm-project

History

Luke Cheeseman f57d7d8237 [AArch64] - Return address signing dwarf support - Reapply changes intially introduced in r343089 - The archtecture info is no longer loaded whenever a DWARFContext is created - The runtimes libraries (santiziers) make use of the dwarf context classes but do not intialise the target info - The architecture of the object can be obtained without loading the target info - Adding a method to the dwarf context to get this information and multiplex the string printing later on Differential Revision: https://reviews.llvm.org/D55774 llvm-svn: 349472		2018-12-18 10:37:42 +00:00
..
AArch64	[AArch64] - Return address signing dwarf support	2018-12-18 10:37:42 +00:00
AMDGPU	AMDGPU: Fix tests using old number for constant address space	2018-09-10 02:54:25 +00:00
ARM	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Generic	[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL	2018-10-01 21:59:45 +00:00
Hexagon	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Mips	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
NVPTX	[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.	2018-01-10 00:56:48 +00:00
PowerPC	[Power9] Allow gpr callee saved spills in prologue to vectors registers	2018-11-09 16:36:24 +00:00
WebAssembly	[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)	2018-05-08 02:02:50 +00:00
X86	[mir] Serialize DILocation inline when not possible to use a metadata reference	2018-12-13 14:25:27 +00:00
README	…

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.