forked from OSchip/llvm-project
637 lines
23 KiB
C++
637 lines
23 KiB
C++
//===----- X86CallFrameOptimization.cpp - Optimize x86 call sequences -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pass that optimizes call sequences on x86.
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// Currently, it converts movs of function parameters onto the stack into
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// pushes. This is beneficial for two main reasons:
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// 1) The push instruction encoding is much smaller than a stack-ptr-based mov.
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// 2) It is possible to push memory arguments directly. So, if the
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// the transformation is performed pre-reg-alloc, it can help relieve
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// register pressure.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86FrameLowering.h"
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#include "X86InstrInfo.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCDwarf.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <iterator>
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using namespace llvm;
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#define DEBUG_TYPE "x86-cf-opt"
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static cl::opt<bool>
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NoX86CFOpt("no-x86-call-frame-opt",
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cl::desc("Avoid optimizing x86 call frames for size"),
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cl::init(false), cl::Hidden);
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namespace llvm {
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void initializeX86CallFrameOptimizationPass(PassRegistry &);
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}
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namespace {
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class X86CallFrameOptimization : public MachineFunctionPass {
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public:
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X86CallFrameOptimization() : MachineFunctionPass(ID) {
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initializeX86CallFrameOptimizationPass(
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*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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static char ID;
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private:
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// Information we know about a particular call site
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struct CallContext {
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CallContext() : FrameSetup(nullptr), ArgStoreVector(4, nullptr) {}
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// Iterator referring to the frame setup instruction
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MachineBasicBlock::iterator FrameSetup;
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// Actual call instruction
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MachineInstr *Call = nullptr;
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// A copy of the stack pointer
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MachineInstr *SPCopy = nullptr;
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// The total displacement of all passed parameters
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int64_t ExpectedDist = 0;
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// The sequence of storing instructions used to pass the parameters
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SmallVector<MachineInstr *, 4> ArgStoreVector;
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// True if this call site has no stack parameters
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bool NoStackParams = false;
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// True if this call site can use push instructions
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bool UsePush = false;
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};
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typedef SmallVector<CallContext, 8> ContextVector;
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bool isLegal(MachineFunction &MF);
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bool isProfitable(MachineFunction &MF, ContextVector &CallSeqMap);
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void collectCallInfo(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, CallContext &Context);
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void adjustCallSequence(MachineFunction &MF, const CallContext &Context);
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MachineInstr *canFoldIntoRegPush(MachineBasicBlock::iterator FrameSetup,
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unsigned Reg);
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enum InstClassification { Convert, Skip, Exit };
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InstClassification classifyInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const X86RegisterInfo &RegInfo,
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DenseSet<unsigned int> &UsedRegs);
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StringRef getPassName() const override { return "X86 Optimize Call Frame"; }
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const X86InstrInfo *TII;
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const X86FrameLowering *TFL;
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const X86Subtarget *STI;
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MachineRegisterInfo *MRI;
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unsigned SlotSize;
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unsigned Log2SlotSize;
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};
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} // end anonymous namespace
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char X86CallFrameOptimization::ID = 0;
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INITIALIZE_PASS(X86CallFrameOptimization, DEBUG_TYPE,
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"X86 Call Frame Optimization", false, false)
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// This checks whether the transformation is legal.
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// Also returns false in cases where it's potentially legal, but
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// we don't even want to try.
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bool X86CallFrameOptimization::isLegal(MachineFunction &MF) {
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if (NoX86CFOpt.getValue())
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return false;
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// We can't encode multiple DW_CFA_GNU_args_size or DW_CFA_def_cfa_offset
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// in the compact unwind encoding that Darwin uses. So, bail if there
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// is a danger of that being generated.
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if (STI->isTargetDarwin() &&
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(!MF.getLandingPads().empty() ||
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(MF.getFunction()->needsUnwindTableEntry() && !TFL->hasFP(MF))))
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return false;
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// It is not valid to change the stack pointer outside the prolog/epilog
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// on 64-bit Windows.
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if (STI->isTargetWin64())
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return false;
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// You would expect straight-line code between call-frame setup and
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// call-frame destroy. You would be wrong. There are circumstances (e.g.
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// CMOV_GR8 expansion of a select that feeds a function call!) where we can
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// end up with the setup and the destroy in different basic blocks.
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// This is bad, and breaks SP adjustment.
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// So, check that all of the frames in the function are closed inside
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// the same block, and, for good measure, that there are no nested frames.
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unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
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unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
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for (MachineBasicBlock &BB : MF) {
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bool InsideFrameSequence = false;
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for (MachineInstr &MI : BB) {
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if (MI.getOpcode() == FrameSetupOpcode) {
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if (InsideFrameSequence)
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return false;
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InsideFrameSequence = true;
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} else if (MI.getOpcode() == FrameDestroyOpcode) {
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if (!InsideFrameSequence)
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return false;
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InsideFrameSequence = false;
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}
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}
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if (InsideFrameSequence)
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return false;
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}
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return true;
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}
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// Check whether this transformation is profitable for a particular
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// function - in terms of code size.
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bool X86CallFrameOptimization::isProfitable(MachineFunction &MF,
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ContextVector &CallSeqVector) {
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// This transformation is always a win when we do not expect to have
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// a reserved call frame. Under other circumstances, it may be either
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// a win or a loss, and requires a heuristic.
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bool CannotReserveFrame = MF.getFrameInfo().hasVarSizedObjects();
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if (CannotReserveFrame)
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return true;
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unsigned StackAlign = TFL->getStackAlignment();
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int64_t Advantage = 0;
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for (auto CC : CallSeqVector) {
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// Call sites where no parameters are passed on the stack
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// do not affect the cost, since there needs to be no
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// stack adjustment.
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if (CC.NoStackParams)
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continue;
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if (!CC.UsePush) {
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// If we don't use pushes for a particular call site,
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// we pay for not having a reserved call frame with an
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// additional sub/add esp pair. The cost is ~3 bytes per instruction,
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// depending on the size of the constant.
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// TODO: Callee-pop functions should have a smaller penalty, because
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// an add is needed even with a reserved call frame.
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Advantage -= 6;
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} else {
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// We can use pushes. First, account for the fixed costs.
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// We'll need a add after the call.
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Advantage -= 3;
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// If we have to realign the stack, we'll also need a sub before
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if (CC.ExpectedDist % StackAlign)
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Advantage -= 3;
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// Now, for each push, we save ~3 bytes. For small constants, we actually,
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// save more (up to 5 bytes), but 3 should be a good approximation.
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Advantage += (CC.ExpectedDist >> Log2SlotSize) * 3;
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}
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}
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return Advantage >= 0;
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}
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bool X86CallFrameOptimization::runOnMachineFunction(MachineFunction &MF) {
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STI = &MF.getSubtarget<X86Subtarget>();
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TII = STI->getInstrInfo();
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TFL = STI->getFrameLowering();
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MRI = &MF.getRegInfo();
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const X86RegisterInfo &RegInfo =
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*static_cast<const X86RegisterInfo *>(STI->getRegisterInfo());
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SlotSize = RegInfo.getSlotSize();
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assert(isPowerOf2_32(SlotSize) && "Expect power of 2 stack slot size");
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Log2SlotSize = Log2_32(SlotSize);
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if (skipFunction(*MF.getFunction()) || !isLegal(MF))
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return false;
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unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
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bool Changed = false;
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ContextVector CallSeqVector;
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for (auto &MBB : MF)
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for (auto &MI : MBB)
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if (MI.getOpcode() == FrameSetupOpcode) {
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CallContext Context;
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collectCallInfo(MF, MBB, MI, Context);
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CallSeqVector.push_back(Context);
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}
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if (!isProfitable(MF, CallSeqVector))
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return false;
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for (auto CC : CallSeqVector) {
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if (CC.UsePush) {
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adjustCallSequence(MF, CC);
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Changed = true;
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}
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}
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return Changed;
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}
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X86CallFrameOptimization::InstClassification
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X86CallFrameOptimization::classifyInstruction(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) {
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if (MI == MBB.end())
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return Exit;
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// The instructions we actually care about are movs onto the stack or special
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// cases of constant-stores to stack
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switch (MI->getOpcode()) {
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case X86::AND16mi8:
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case X86::AND32mi8:
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case X86::AND64mi8: {
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MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
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return ImmOp.getImm() == 0 ? Convert : Exit;
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}
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case X86::OR16mi8:
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case X86::OR32mi8:
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case X86::OR64mi8: {
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MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
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return ImmOp.getImm() == -1 ? Convert : Exit;
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}
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case X86::MOV32mi:
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case X86::MOV32mr:
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case X86::MOV64mi32:
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case X86::MOV64mr:
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return Convert;
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}
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// Not all calling conventions have only stack MOVs between the stack
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// adjust and the call.
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// We want to tolerate other instructions, to cover more cases.
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// In particular:
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// a) PCrel calls, where we expect an additional COPY of the basereg.
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// b) Passing frame-index addresses.
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// c) Calling conventions that have inreg parameters. These generate
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// both copies and movs into registers.
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// To avoid creating lots of special cases, allow any instruction
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// that does not write into memory, does not def or use the stack
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// pointer, and does not def any register that was used by a preceding
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// push.
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// (Reading from memory is allowed, even if referenced through a
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// frame index, since these will get adjusted properly in PEI)
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// The reason for the last condition is that the pushes can't replace
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// the movs in place, because the order must be reversed.
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// So if we have a MOV32mr that uses EDX, then an instruction that defs
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// EDX, and then the call, after the transformation the push will use
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// the modified version of EDX, and not the original one.
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// Since we are still in SSA form at this point, we only need to
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// make sure we don't clobber any *physical* registers that were
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// used by an earlier mov that will become a push.
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if (MI->isCall() || MI->mayStore())
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return Exit;
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for (const MachineOperand &MO : MI->operands()) {
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if (!MO.isReg())
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continue;
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unsigned int Reg = MO.getReg();
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if (!RegInfo.isPhysicalRegister(Reg))
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continue;
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if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister()))
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return Exit;
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if (MO.isDef()) {
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for (unsigned int U : UsedRegs)
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if (RegInfo.regsOverlap(Reg, U))
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return Exit;
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}
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}
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return Skip;
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}
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void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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CallContext &Context) {
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// Check that this particular call sequence is amenable to the
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// transformation.
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const X86RegisterInfo &RegInfo =
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*static_cast<const X86RegisterInfo *>(STI->getRegisterInfo());
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// We expect to enter this at the beginning of a call sequence
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assert(I->getOpcode() == TII->getCallFrameSetupOpcode());
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MachineBasicBlock::iterator FrameSetup = I++;
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Context.FrameSetup = FrameSetup;
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// How much do we adjust the stack? This puts an upper bound on
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// the number of parameters actually passed on it.
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unsigned int MaxAdjust = TII->getFrameSize(*FrameSetup) >> Log2SlotSize;
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// A zero adjustment means no stack parameters
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if (!MaxAdjust) {
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Context.NoStackParams = true;
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return;
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}
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// Skip over DEBUG_VALUE.
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// For globals in PIC mode, we can have some LEAs here. Skip them as well.
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// TODO: Extend this to something that covers more cases.
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while (I->getOpcode() == X86::LEA32r || I->isDebugValue())
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++I;
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unsigned StackPtr = RegInfo.getStackRegister();
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auto StackPtrCopyInst = MBB.end();
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// SelectionDAG (but not FastISel) inserts a copy of ESP into a virtual
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// register. If it's there, use that virtual register as stack pointer
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// instead. Also, we need to locate this instruction so that we can later
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// safely ignore it while doing the conservative processing of the call chain.
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// The COPY can be located anywhere between the call-frame setup
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// instruction and its first use. We use the call instruction as a boundary
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// because it is usually cheaper to check if an instruction is a call than
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// checking if an instruction uses a register.
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for (auto J = I; !J->isCall(); ++J)
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if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
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J->getOperand(1).getReg() == StackPtr) {
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StackPtrCopyInst = J;
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Context.SPCopy = &*J++;
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StackPtr = Context.SPCopy->getOperand(0).getReg();
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break;
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}
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// Scan the call setup sequence for the pattern we're looking for.
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// We only handle a simple case - a sequence of store instructions that
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// push a sequence of stack-slot-aligned values onto the stack, with
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// no gaps between them.
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if (MaxAdjust > 4)
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Context.ArgStoreVector.resize(MaxAdjust, nullptr);
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DenseSet<unsigned int> UsedRegs;
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for (InstClassification Classification = Skip; Classification != Exit; ++I) {
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// If this is the COPY of the stack pointer, it's ok to ignore.
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if (I == StackPtrCopyInst)
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continue;
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Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs);
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if (Classification != Convert)
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continue;
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// We know the instruction has a supported store opcode.
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// We only want movs of the form:
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// mov imm/reg, k(%StackPtr)
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// If we run into something else, bail.
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// Note that AddrBaseReg may, counter to its name, not be a register,
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// but rather a frame index.
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// TODO: Support the fi case. This should probably work now that we
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// have the infrastructure to track the stack pointer within a call
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// sequence.
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if (!I->getOperand(X86::AddrBaseReg).isReg() ||
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(I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
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!I->getOperand(X86::AddrScaleAmt).isImm() ||
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(I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
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(I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
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(I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
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!I->getOperand(X86::AddrDisp).isImm())
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return;
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int64_t StackDisp = I->getOperand(X86::AddrDisp).getImm();
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assert(StackDisp >= 0 &&
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"Negative stack displacement when passing parameters");
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// We really don't want to consider the unaligned case.
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if (StackDisp & (SlotSize - 1))
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return;
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StackDisp >>= Log2SlotSize;
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assert((size_t)StackDisp < Context.ArgStoreVector.size() &&
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"Function call has more parameters than the stack is adjusted for.");
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// If the same stack slot is being filled twice, something's fishy.
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if (Context.ArgStoreVector[StackDisp] != nullptr)
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return;
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Context.ArgStoreVector[StackDisp] = &*I;
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for (const MachineOperand &MO : I->uses()) {
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if (!MO.isReg())
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continue;
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unsigned int Reg = MO.getReg();
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if (RegInfo.isPhysicalRegister(Reg))
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UsedRegs.insert(Reg);
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}
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}
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--I;
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// We now expect the end of the sequence. If we stopped early,
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// or reached the end of the block without finding a call, bail.
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if (I == MBB.end() || !I->isCall())
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return;
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Context.Call = &*I;
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if ((++I)->getOpcode() != TII->getCallFrameDestroyOpcode())
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return;
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// Now, go through the vector, and see that we don't have any gaps,
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// but only a series of storing instructions.
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auto MMI = Context.ArgStoreVector.begin(), MME = Context.ArgStoreVector.end();
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for (; MMI != MME; ++MMI, Context.ExpectedDist += SlotSize)
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if (*MMI == nullptr)
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break;
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// If the call had no parameters, do nothing
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if (MMI == Context.ArgStoreVector.begin())
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return;
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// We are either at the last parameter, or a gap.
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// Make sure it's not a gap
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for (; MMI != MME; ++MMI)
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if (*MMI != nullptr)
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return;
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Context.UsePush = true;
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}
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void X86CallFrameOptimization::adjustCallSequence(MachineFunction &MF,
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const CallContext &Context) {
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// Ok, we can in fact do the transformation for this call.
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// Do not remove the FrameSetup instruction, but adjust the parameters.
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// PEI will end up finalizing the handling of this.
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MachineBasicBlock::iterator FrameSetup = Context.FrameSetup;
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MachineBasicBlock &MBB = *(FrameSetup->getParent());
|
|
TII->setFrameAdjustment(*FrameSetup, Context.ExpectedDist);
|
|
|
|
DebugLoc DL = FrameSetup->getDebugLoc();
|
|
bool Is64Bit = STI->is64Bit();
|
|
// Now, iterate through the vector in reverse order, and replace the store to
|
|
// stack with pushes. MOVmi/MOVmr doesn't have any defs, so no need to
|
|
// replace uses.
|
|
for (int Idx = (Context.ExpectedDist >> Log2SlotSize) - 1; Idx >= 0; --Idx) {
|
|
MachineBasicBlock::iterator Store = *Context.ArgStoreVector[Idx];
|
|
MachineOperand PushOp = Store->getOperand(X86::AddrNumOperands);
|
|
MachineBasicBlock::iterator Push = nullptr;
|
|
unsigned PushOpcode;
|
|
switch (Store->getOpcode()) {
|
|
default:
|
|
llvm_unreachable("Unexpected Opcode!");
|
|
case X86::AND16mi8:
|
|
case X86::AND32mi8:
|
|
case X86::AND64mi8:
|
|
case X86::OR16mi8:
|
|
case X86::OR32mi8:
|
|
case X86::OR64mi8:
|
|
case X86::MOV32mi:
|
|
case X86::MOV64mi32:
|
|
PushOpcode = Is64Bit ? X86::PUSH64i32 : X86::PUSHi32;
|
|
// If the operand is a small (8-bit) immediate, we can use a
|
|
// PUSH instruction with a shorter encoding.
|
|
// Note that isImm() may fail even though this is a MOVmi, because
|
|
// the operand can also be a symbol.
|
|
if (PushOp.isImm()) {
|
|
int64_t Val = PushOp.getImm();
|
|
if (isInt<8>(Val))
|
|
PushOpcode = Is64Bit ? X86::PUSH64i8 : X86::PUSH32i8;
|
|
}
|
|
Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode)).add(PushOp);
|
|
break;
|
|
case X86::MOV32mr:
|
|
case X86::MOV64mr: {
|
|
unsigned int Reg = PushOp.getReg();
|
|
|
|
// If storing a 32-bit vreg on 64-bit targets, extend to a 64-bit vreg
|
|
// in preparation for the PUSH64. The upper 32 bits can be undef.
|
|
if (Is64Bit && Store->getOpcode() == X86::MOV32mr) {
|
|
unsigned UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass);
|
|
Reg = MRI->createVirtualRegister(&X86::GR64RegClass);
|
|
BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg);
|
|
BuildMI(MBB, Context.Call, DL, TII->get(X86::INSERT_SUBREG), Reg)
|
|
.addReg(UndefReg)
|
|
.add(PushOp)
|
|
.addImm(X86::sub_32bit);
|
|
}
|
|
|
|
// If PUSHrmm is not slow on this target, try to fold the source of the
|
|
// push into the instruction.
|
|
bool SlowPUSHrmm = STI->isAtom() || STI->isSLM();
|
|
|
|
// Check that this is legal to fold. Right now, we're extremely
|
|
// conservative about that.
|
|
MachineInstr *DefMov = nullptr;
|
|
if (!SlowPUSHrmm && (DefMov = canFoldIntoRegPush(FrameSetup, Reg))) {
|
|
PushOpcode = Is64Bit ? X86::PUSH64rmm : X86::PUSH32rmm;
|
|
Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode));
|
|
|
|
unsigned NumOps = DefMov->getDesc().getNumOperands();
|
|
for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
|
|
Push->addOperand(DefMov->getOperand(i));
|
|
|
|
DefMov->eraseFromParent();
|
|
} else {
|
|
PushOpcode = Is64Bit ? X86::PUSH64r : X86::PUSH32r;
|
|
Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode))
|
|
.addReg(Reg)
|
|
.getInstr();
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
// For debugging, when using SP-based CFA, we need to adjust the CFA
|
|
// offset after each push.
|
|
// TODO: This is needed only if we require precise CFA.
|
|
if (!TFL->hasFP(MF))
|
|
TFL->BuildCFI(
|
|
MBB, std::next(Push), DL,
|
|
MCCFIInstruction::createAdjustCfaOffset(nullptr, SlotSize));
|
|
|
|
MBB.erase(Store);
|
|
}
|
|
|
|
// The stack-pointer copy is no longer used in the call sequences.
|
|
// There should not be any other users, but we can't commit to that, so:
|
|
if (Context.SPCopy && MRI->use_empty(Context.SPCopy->getOperand(0).getReg()))
|
|
Context.SPCopy->eraseFromParent();
|
|
|
|
// Once we've done this, we need to make sure PEI doesn't assume a reserved
|
|
// frame.
|
|
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
|
FuncInfo->setHasPushSequences(true);
|
|
}
|
|
|
|
MachineInstr *X86CallFrameOptimization::canFoldIntoRegPush(
|
|
MachineBasicBlock::iterator FrameSetup, unsigned Reg) {
|
|
// Do an extremely restricted form of load folding.
|
|
// ISel will often create patterns like:
|
|
// movl 4(%edi), %eax
|
|
// movl 8(%edi), %ecx
|
|
// movl 12(%edi), %edx
|
|
// movl %edx, 8(%esp)
|
|
// movl %ecx, 4(%esp)
|
|
// movl %eax, (%esp)
|
|
// call
|
|
// Get rid of those with prejudice.
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
return nullptr;
|
|
|
|
// Make sure this is the only use of Reg.
|
|
if (!MRI->hasOneNonDBGUse(Reg))
|
|
return nullptr;
|
|
|
|
MachineInstr &DefMI = *MRI->getVRegDef(Reg);
|
|
|
|
// Make sure the def is a MOV from memory.
|
|
// If the def is in another block, give up.
|
|
if ((DefMI.getOpcode() != X86::MOV32rm &&
|
|
DefMI.getOpcode() != X86::MOV64rm) ||
|
|
DefMI.getParent() != FrameSetup->getParent())
|
|
return nullptr;
|
|
|
|
// Make sure we don't have any instructions between DefMI and the
|
|
// push that make folding the load illegal.
|
|
for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I)
|
|
if (I->isLoadFoldBarrier())
|
|
return nullptr;
|
|
|
|
return &DefMI;
|
|
}
|
|
|
|
FunctionPass *llvm::createX86CallFrameOptimization() {
|
|
return new X86CallFrameOptimization();
|
|
}
|