Simon Pilgrim 9d1721ce39 [X86][SSE] Prefer PACKUS(AND(),AND()) to SHUFFLE(PSHUFB(),PSHUFB()) on pre-AVX2 targets ... As discussed on PR31443, we should be trying to use PACKUS for binary truncation patterns to reduce the number of shuffles. The plan is to support AVX2+ targets once we've worked around PR45315 - we fail to peek through a VBROADCAST_LOAD mask to recognise zero upper bits in a PACKUS pattern. We should also be able to add support for v8i16 and possibly 256/512-bit vectors as well.		2020-03-26 15:47:43 +00:00
..
AArch64	[AArch64][SVE] Implement structured store intrinsics	2020-03-26 09:34:51 +00:00
AMDGPU	[AMDGPU] Fixed function traversal in attribute propagation	2020-03-25 18:47:09 -07:00
ARC	…
ARM	[ARM] Move ConstantIsland and LowOverheadLoops Passes.	2020-03-25 16:49:21 +01:00
AVR	[AVR] Fix incorrect register state for LDRdPtr	2020-03-03 17:34:54 +08:00
BPF	[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options	2020-03-15 17:46:23 -07:00
Generic	[NFC] Add missing REQUIRES clause to a test	2020-03-18 16:35:10 +03:00
Hexagon	Revert "Include static prof data when collecting loop BBs"	2020-03-24 09:41:16 -07:00
Inputs	…
Lanai	Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""	2020-02-13 10:16:06 -08:00
MIR	[AMDGPU] Move frame pointer from s34 to s33	2020-03-19 15:35:16 -04:00
MSP430	…
Mips	[GlobalISel] combine G_TRUNC with G_MERGE_VALUES	2020-03-16 14:42:01 +01:00
NVPTX	ARM: Fixup some tests using denormal-fp-math attribute	2020-03-10 14:02:06 -04:00
PowerPC	[PPCInstPrinter] Change printBranchOperand(calltarget) to print the target address in hexadecimal form	2020-03-26 08:32:29 -07:00
RISCV	[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w	2020-03-20 09:42:24 +00:00
SPARC	[Sparc] Fix incorrect operand for matching CMPri pattern	2020-03-02 11:36:32 +08:00
SystemZ	[SystemZ] Improve foldMemoryOperandImpl()	2020-03-25 16:21:08 +01:00
Thumb	[DAGCombine] Skip PostInc combine with later users	2020-03-23 08:39:53 +00:00
Thumb2	[ARM] Sink splats to vector float instructions	2020-03-26 09:02:18 +00:00
VE	[VE] Target-specific bit size for sjljehprepare	2020-03-10 17:51:16 +01:00
WebAssembly	[WebAssembly] Support swiftself and swifterror for WebAssembly target	2020-03-19 17:39:52 -07:00
WinCFGuard	…
WinEH	…
X86	[X86][SSE] Prefer PACKUS(AND(),AND()) to SHUFFLE(PSHUFB(),PSHUFB()) on pre-AVX2 targets	2020-03-26 15:47:43 +00:00
XCore	[XCore] Add instruction pattern for bitrev	2020-02-21 09:28:49 +08:00