forked from OSchip/llvm-project
60 lines
1.9 KiB
C++
60 lines
1.9 KiB
C++
//===-- HexagonMCCodeEmitter.h - Hexagon Target Descriptions ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief Definition for classes that emit Hexagon machine code from MCInsts
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///
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//===----------------------------------------------------------------------===//
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#ifndef HEXAGONMCCODEEMITTER_H
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#define HEXAGONMCCODEEMITTER_H
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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class HexagonMCCodeEmitter : public MCCodeEmitter {
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MCContext &MCT;
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MCInstrInfo const &MCII;
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public:
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HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT);
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MCSubtargetInfo const &getSubtargetInfo() const;
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void EncodeInstruction(MCInst const &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const override;
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// \brief TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(MCInst const &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const;
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/// \brief Return binary encoding of operand.
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unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const;
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private:
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HexagonMCCodeEmitter(HexagonMCCodeEmitter const &) = delete;
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void operator=(HexagonMCCodeEmitter const &) = delete;
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}; // class HexagonMCCodeEmitter
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} // namespace llvm
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#endif /* HEXAGONMCCODEEMITTER_H */
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