Nicolas Vasilache a89d8c0a1a Port Tablegen'd reference implementation of Add to declarative builders. ... PiperOrigin-RevId: 238977252		2019-03-29 17:22:36 -07:00
..
AffineOps	Rename BlockList into Region	2019-03-29 17:18:04 -07:00
Analysis	Rename BlockList into Region	2019-03-29 17:18:04 -07:00
Dialect	Allow input and output to have different element types for broadcastable ops	2019-03-29 17:12:26 -07:00
EDSC	Port Tablegen'd reference implementation of Add to declarative builders.	2019-03-29 17:22:36 -07:00
ExecutionEngine	Move `createConvertToLLVMIRPass()` to its own header matching the target library clients need to link	2019-03-29 17:11:07 -07:00
IR	Move getSuccessorOperandIndex out of line.	2019-03-29 17:21:19 -07:00
LLVMIR	Move `createConvertToLLVMIRPass()` to its own header matching the target library clients need to link	2019-03-29 17:11:07 -07:00
Parser	Add an 'Instruction::create' overload that accepts an existing NamedAttributeList. This avoids the need to unique an attribute list if one already exists, e.g. when cloning an existing instruction.	2019-03-29 17:18:38 -07:00
Pass	Moving the IR printing and execution timing options out of mlir-opt and into lib/Pass. We now expose two methods: registerPassManagerCLOptions and applyPassManagerCLOptions; to allow for multiple different users (mlir-opt, etc.) to opt-in to this common functionality.	2019-03-29 17:21:50 -07:00
StandardOps	Set the namespace of the StandardOps dialect to "std", but add a special case to the parser to allow parsing standard operations without the "std" prefix. This will now allow for the standard dialect to be looked up dynamically by name.	2019-03-29 16:54:20 -07:00
SuperVectorOps	Remove remaining references to OperationInst in all directories except for lib/Transforms.	2019-03-29 16:10:38 -07:00
Support	Extract openInputFile() into Support/FileUtilities	2019-03-29 15:09:11 -07:00
TableGen	[TableGen] Support nested dag attributes arguments in the result pattern	2019-03-29 17:15:57 -07:00
Target/LLVMIR	TableGen most of the LLVM IR Dialect to LLVM IR conversions	2019-03-29 17:04:50 -07:00
Transforms	Port Tablegen'd reference implementation of Add to declarative builders.	2019-03-29 17:22:36 -07:00
Translation	Separate translators into "from MLIR" and "to MLIR".	2019-03-29 14:06:33 -07:00