llvm-project/polly/test/CodeGen/simple_vec_stride_one___%1-...

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{
"name": "%1 => %5",
"context": "{ [] }",
"statements": [{
"name": "Stmt_2",
"domain": "{ Stmt_2[i0] : i0 >= 0 and i0 <= 3 }",
"schedule": "{ Stmt_2[i0] -> scattering[0, 4i0, 0] }",
"accesses": [{
"kind": "read",
"relation": "{ Stmt_2[i0] -> MemRef_A[i0] }"
},
{
"kind": "write",
"relation": "{ Stmt_2[i0] -> MemRef_B[i0] }"
}]
}]
}