forked from OSchip/llvm-project
279 lines
8.5 KiB
LLVM
279 lines
8.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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target datalayout = "n8:16:32"
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; Given pattern:
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; (trunc (x << Q) to iDst) << K
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; we should rewrite it as
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; (trunc (x << (Q+K)) to iDst) iff (Q+K) u< iDst
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; This is only valid for shl.
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; THIS FOLD DOES *NOT* REQUIRE ANY 'nuw'/`nsw` FLAGS!
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; Basic scalar test
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define i16 @t0(i32 %x, i16 %y) {
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; CHECK-LABEL: @t0(
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; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -24
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {
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; CHECK-LABEL: @t1_vec_splat(
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; CHECK-NEXT: [[X_TR:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i16>
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; CHECK-NEXT: [[T5:%.*]] = shl <2 x i16> [[X_TR]], <i16 8, i16 8>
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; CHECK-NEXT: ret <2 x i16> [[T5]]
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;
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%t0 = sub <2 x i16> <i16 32, i16 32>, %y
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%t1 = zext <2 x i16> %t0 to <2 x i32>
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%t2 = shl <2 x i32> %x, %t1
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%t3 = trunc <2 x i32> %t2 to <2 x i16>
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%t4 = add <2 x i16> %y, <i16 -24, i16 -24>
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%t5 = shl <2 x i16> %t3, %t4
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ret <2 x i16> %t5
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}
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define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {
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; CHECK-LABEL: @t2_vec_nonsplat(
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; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 30>
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; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[T5]]
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;
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%t0 = sub <2 x i16> <i16 32, i16 30>, %y
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%t1 = zext <2 x i16> %t0 to <2 x i32>
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%t2 = shl <2 x i32> %x, %t1
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%t3 = trunc <2 x i32> %t2 to <2 x i16>
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%t4 = add <2 x i16> %y, <i16 -24, i16 0>
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%t5 = shl <2 x i16> %t3, %t4
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ret <2 x i16> %t5
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}
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; Basic vector tests
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define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t3_vec_nonsplat_undef0(
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; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = shl <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -24, i16 -24, i16 -24>
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%t5 = shl <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t4_vec_nonsplat_undef1(
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; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = shl <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
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%t5 = shl <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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define <3 x i16> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t5_vec_nonsplat_undef1(
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; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = shl <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
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%t5 = shl <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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; One-use tests
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declare void @use16(i16)
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declare void @use32(i32)
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define i16 @t6_extrause0(i32 %x, i16 %y) {
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; CHECK-LABEL: @t6_extrause0(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: call void @use16(i16 [[T3]])
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; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X]] to i16
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -24
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call void @use16(i16 %t3)
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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define i16 @t7_extrause1(i32 %x, i16 %y) {
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; CHECK-LABEL: @t7_extrause1(
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y:%.*]], -24
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; CHECK-NEXT: call void @use16(i16 [[T4]])
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; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -24
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call void @use16(i16 %t4)
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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define i16 @t8_extrause2(i32 %x, i16 %y) {
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; CHECK-LABEL: @t8_extrause2(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -24
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; CHECK-NEXT: call void @use16(i16 [[T3]])
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; CHECK-NEXT: call void @use16(i16 [[T4]])
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -24
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call void @use16(i16 %t3)
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call void @use16(i16 %t4)
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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; No 'nuw'/'nsw' flags are to be propagated!
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; But we can't test that, such IR does not reach that code.
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; Negative tests
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; Can't fold, total shift would be 32
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define i16 @n11(i32 %x, i16 %y) {
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; CHECK-LABEL: @n11(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 30, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -31
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 30, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -31
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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; Bit width mismatch of shift amount
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@Y32 = global i32 42
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@Y16 = global i16 42
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define i16 @t01(i32 %x) {
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; CHECK-LABEL: @t01(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], ptrtoint (i32* @Y32 to i32)
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; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[T0]] to i16
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; CHECK-NEXT: [[T2:%.*]] = shl i16 [[T1]], ptrtoint (i16* @Y16 to i16)
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; CHECK-NEXT: ret i16 [[T2]]
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;
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%t0 = shl i32 %x, ptrtoint (i32* @Y32 to i32)
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%t1 = trunc i32 %t0 to i16
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%t2 = shl i16 %t1, ptrtoint (i16* @Y16 to i16)
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ret i16 %t2
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}
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define i16 @shl_tr_shl_constant_shift_amount_uses(i32 %x) {
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; CHECK-LABEL: @shl_tr_shl_constant_shift_amount_uses(
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 3
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; CHECK-NEXT: call void @use32(i32 [[SHL]])
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; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[SHL]] to i16
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; CHECK-NEXT: call void @use16(i16 [[TR]])
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; CHECK-NEXT: [[R:%.*]] = shl i16 [[TR]], 4
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; CHECK-NEXT: ret i16 [[R]]
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;
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%shl = shl i32 %x, 3
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call void @use32(i32 %shl)
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%tr = trunc i32 %shl to i16
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call void @use16(i16 %tr)
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%r = shl i16 %tr, 4
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ret i16 %r
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}
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; This would infinite loop because we did not process the
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; poison shift before trying to fold shift-of-shift. To reach
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; the problematic transform, it needs a datalayout to specify
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; that the narrow types are legal, but i64 is not.
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define i1 @PR51657(i64 %x) {
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; CHECK-LABEL: @PR51657(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 undef, label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: br label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: ret i1 true
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;
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entry:
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br i1 undef, label %cond.false, label %cond.end
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cond.false:
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%shl = shl i64 %x, 64
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%conv26 = trunc i64 %shl to i32
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%t1 = trunc i64 %shl to i8
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %conv26, %cond.false ], [ 0, %entry ]
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%t2 = phi i8 [ %t1, %cond.false ], [ 0, %entry ]
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%conv27 = sext i8 %t2 to i32
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%eq = icmp eq i32 %cond, %conv27
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ret i1 %eq
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}
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define i16 @extra_use_on_first_shift(i32 %x) {
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; CHECK-LABEL: @extra_use_on_first_shift(
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; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 3
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; CHECK-NEXT: call void @use32(i32 [[A]])
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; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[A]] to i16
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; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[TR]], 6
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; CHECK-NEXT: ret i16 [[SH]]
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;
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%a = ashr i32 %x, 3
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call void @use32(i32 %a)
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%tr = trunc i32 %a to i16
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%sh = lshr i16 %tr, 6
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ret i16 %sh
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}
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