llvm-project/llvm/test/MC/Disassembler/AMDGPU
Matt Arsenault 0084adc516 AMDGPU: Add Vega12 and Vega20
Changes by
  Matt Arsenault
  Konstantin Zhuravlyov

llvm-svn: 331215
2018-04-30 19:08:16 +00:00
..
aperture-regs.ll
buf_fmt_packed_d16.txt AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace. 2018-01-30 16:42:40 +00:00
buf_fmt_unpacked_d16.txt AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace. 2018-01-30 16:42:40 +00:00
dpp_gfx9.txt [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32 2018-04-11 13:13:30 +00:00
dpp_vi.txt [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32 2018-04-16 12:41:38 +00:00
ds_vi.txt [AMDGPU][MC] Added ds_add_src2_f32 2018-03-28 16:21:56 +00:00
exp_vi.txt [AMDGPU][MC] Fixed bugs in export instruction 2017-05-19 13:36:09 +00:00
flat_gfx9.txt [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiers 2017-12-29 13:55:11 +00:00
flat_vi.txt AMDGPU: Remove tfe bit from flat instruction definitions 2017-05-11 17:38:33 +00:00
gfx8_dasm_all.txt [AMDGPU][MC] Corrected default values for unused SDWA operands 2018-03-16 15:40:27 +00:00
gfx9_dasm_all.txt [AMDGPU][MC] Corrected default values for unused SDWA operands 2018-03-16 15:40:27 +00:00
lit.local.cfg
literal16_vi.txt [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler output 2017-05-10 13:00:28 +00:00
mac.txt
mad_mix.txt AMDGPU: Add Vega12 and Vega20 2018-04-30 19:08:16 +00:00
mimg_vi.txt [AMDGPU][MC] Added PCK variants of image load/store instructions 2018-03-28 15:44:16 +00:00
mov.txt
mtbuf_vi.txt [AMDGPU] Add intrinsics for tbuffer load and store 2017-06-22 16:29:22 +00:00
mubuf_gfx9.txt [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x 2018-03-28 14:53:13 +00:00
mubuf_vi.txt [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction 2018-03-12 17:29:24 +00:00
nop.txt
sdwa_gfx9.txt [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32 2018-04-16 12:41:38 +00:00
sdwa_vi.txt [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32 2018-04-16 12:41:38 +00:00
si-support.txt
smem_gfx9.txt [AMDGPU][MC][GFX9] Added s_dcache_discard* instructions 2018-04-06 15:08:42 +00:00
smem_vi.txt [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions 2018-04-06 15:48:39 +00:00
smrd_vi.txt
sop1_gfx9.txt [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate* 2018-04-06 16:35:11 +00:00
sop1_vi.txt [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support 2018-01-10 14:22:19 +00:00
sop2_gfx9.txt [AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32 2018-04-09 13:10:33 +00:00
sop2_vi.txt
sopc_vi.txt [AMDGPU][MC] Corrected disassembler to decode instructions with 2 literals 2017-05-19 14:27:52 +00:00
sopk_gfx9.txt [AMDGPU][MC][GFX9] Added s_call_b64 2018-04-06 18:24:49 +00:00
sopk_vi.txt
sopp_vi.txt
trap_gfx9.txt [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers 2017-12-22 15:18:06 +00:00
trap_vi.txt [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers 2017-12-22 15:18:06 +00:00
vintrp.txt [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes 2018-03-16 16:38:04 +00:00
vop1.txt
vop1_gfx9.txt [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32 2018-04-11 13:13:30 +00:00
vop1_vi.txt
vop2_vi.txt [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 2017-11-20 18:24:21 +00:00
vop3_gfx9.txt [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32 2018-04-11 13:13:30 +00:00
vop3_vi.txt [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes 2017-08-16 13:51:56 +00:00
vopc_vi.txt