forked from OSchip/llvm-project
80 lines
3.3 KiB
ArmAsm
80 lines
3.3 KiB
ArmAsm
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s 2>%t | FileCheck %s
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// RUN: FileCheck --check-prefix=CHECK-ERROR %s <%t
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//------------------------------------------------------------------------------
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// Load acquire / store release
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//------------------------------------------------------------------------------
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ldlarb w0,[x1]
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ldlarh w0,[x1]
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ldlar w0,[x1]
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ldlar x0,[x1]
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// CHECK: ldlarb w0, [x1] // encoding: [0x20,0x7c,0xdf,0x08]
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// CHECK: ldlarh w0, [x1] // encoding: [0x20,0x7c,0xdf,0x48]
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// CHECK: ldlar w0, [x1] // encoding: [0x20,0x7c,0xdf,0x88]
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// CHECK: ldlar x0, [x1] // encoding: [0x20,0x7c,0xdf,0xc8]
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stllrb w0,[x1]
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stllrh w0,[x1]
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stllr w0,[x1]
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stllr x0,[x1]
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// CHECK: stllrb w0, [x1] // encoding: [0x20,0x7c,0x9f,0x08]
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// CHECK: stllrh w0, [x1] // encoding: [0x20,0x7c,0x9f,0x48]
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// CHECK: stllr w0, [x1] // encoding: [0x20,0x7c,0x9f,0x88]
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// CHECK: stllr x0, [x1] // encoding: [0x20,0x7c,0x9f,0xc8]
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msr LORSA_EL1, x0
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msr LOREA_EL1, x0
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msr LORN_EL1, x0
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msr LORC_EL1, x0
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mrs x0, LORID_EL1
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// CHECK: msr LORSA_EL1, x0 // encoding: [0x00,0xa4,0x18,0xd5]
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// CHECK: msr LOREA_EL1, x0 // encoding: [0x20,0xa4,0x18,0xd5]
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// CHECK: msr LORN_EL1, x0 // encoding: [0x40,0xa4,0x18,0xd5]
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// CHECK: msr LORC_EL1, x0 // encoding: [0x60,0xa4,0x18,0xd5]
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// CHECK: mrs x0, LORID_EL1 // encoding: [0xe0,0xa4,0x38,0xd5]
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ldlarb w0,[w1]
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ldlarh x0,[x1]
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stllrb w0,[w1]
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stllrh x0,[x1]
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stllr w0,[w1]
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msr LORSA_EL1, #0
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msr LOREA_EL1, #0
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msr LORN_EL1, #0
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msr LORC_EL1, #0
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msr LORID_EL1, x0
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mrs LORID_EL1, #0
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: ldlarb w0,[w1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: ldlarh x0,[x1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: stllrb w0,[w1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: stllrh x0,[x1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: stllr w0,[w1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: msr LORSA_EL1, #0
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: msr LOREA_EL1, #0
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: msr LORN_EL1, #0
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: msr LORC_EL1, #0
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: expected writable system register or pstate
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// CHECK-ERROR: msr LORID_EL1, x0
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: mrs LORID_EL1, #0
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// CHECK-ERROR: ^
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