forked from OSchip/llvm-project
276 lines
9.7 KiB
LLVM
276 lines
9.7 KiB
LLVM
; Test basic EfficiencySanitizer working set instrumentation.
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;
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; RUN: opt < %s -esan -esan-working-set -S | FileCheck %s
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Intra-cache-line
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define i8 @aligned1(i8* %a) {
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entry:
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%tmp1 = load i8, i8* %a, align 1
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ret i8 %tmp1
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; CHECK: @llvm.global_ctors = {{.*}}@esan.module_ctor
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; CHECK: %0 = ptrtoint i8* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i8, i8* %a, align 1
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; CHECK-NEXT: ret i8 %tmp1
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}
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define i16 @aligned2(i16* %a) {
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entry:
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%tmp1 = load i16, i16* %a, align 2
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ret i16 %tmp1
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; CHECK: %0 = ptrtoint i16* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i16, i16* %a, align 2
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; CHECK-NEXT: ret i16 %tmp1
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}
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define i32 @aligned4(i32* %a) {
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entry:
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%tmp1 = load i32, i32* %a, align 4
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ret i32 %tmp1
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; CHECK: %0 = ptrtoint i32* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i32, i32* %a, align 4
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; CHECK-NEXT: ret i32 %tmp1
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}
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define i64 @aligned8(i64* %a) {
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entry:
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%tmp1 = load i64, i64* %a, align 8
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ret i64 %tmp1
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; CHECK: %0 = ptrtoint i64* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i64, i64* %a, align 8
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; CHECK-NEXT: ret i64 %tmp1
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}
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define i128 @aligned16(i128* %a) {
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entry:
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%tmp1 = load i128, i128* %a, align 16
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ret i128 %tmp1
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; CHECK: %0 = ptrtoint i128* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i128, i128* %a, align 16
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; CHECK-NEXT: ret i128 %tmp1
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Not guaranteed to be intra-cache-line, but our defaults are to
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; assume they are:
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define i16 @unaligned2(i16* %a) {
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entry:
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%tmp1 = load i16, i16* %a, align 1
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ret i16 %tmp1
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; CHECK: %0 = ptrtoint i16* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i16, i16* %a, align 1
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; CHECK-NEXT: ret i16 %tmp1
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}
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define i32 @unaligned4(i32* %a) {
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entry:
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%tmp1 = load i32, i32* %a, align 2
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ret i32 %tmp1
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; CHECK: %0 = ptrtoint i32* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i32, i32* %a, align 2
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; CHECK-NEXT: ret i32 %tmp1
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}
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define i64 @unaligned8(i64* %a) {
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entry:
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%tmp1 = load i64, i64* %a, align 4
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ret i64 %tmp1
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; CHECK: %0 = ptrtoint i64* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i64, i64* %a, align 4
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; CHECK-NEXT: ret i64 %tmp1
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}
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define i128 @unaligned16(i128* %a) {
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entry:
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%tmp1 = load i128, i128* %a, align 8
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ret i128 %tmp1
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; CHECK: %0 = ptrtoint i128* %a to i64
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; CHECK-NEXT: %1 = and i64 %0, 17592186044415
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; CHECK-NEXT: %2 = add i64 %1, 1337006139375616
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; CHECK-NEXT: %3 = lshr i64 %2, 6
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; CHECK-NEXT: %4 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: %5 = load i8, i8* %4
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; CHECK-NEXT: %6 = and i8 %5, -127
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; CHECK-NEXT: %7 = icmp ne i8 %6, -127
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; CHECK-NEXT: br i1 %7, label %8, label %11
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; CHECK: %9 = or i8 %5, -127
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; CHECK-NEXT: %10 = inttoptr i64 %3 to i8*
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; CHECK-NEXT: store i8 %9, i8* %10
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; CHECK-NEXT: br label %11
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; CHECK: %tmp1 = load i128, i128* %a, align 8
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; CHECK-NEXT: ret i128 %tmp1
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Ensure that esan converts intrinsics to calls:
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1)
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declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1)
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1)
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define void @memCpyTest(i8* nocapture %x, i8* nocapture %y) {
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entry:
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %x, i8* align 4 %y, i64 16, i1 false)
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ret void
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; CHECK: define void @memCpyTest
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; CHECK: call i8* @memcpy
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; CHECK: ret void
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}
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define void @memMoveTest(i8* nocapture %x, i8* nocapture %y) {
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entry:
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tail call void @llvm.memmove.p0i8.p0i8.i64(i8* align 4 %x, i8* align 4 %y, i64 16, i1 false)
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ret void
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; CHECK: define void @memMoveTest
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; CHECK: call i8* @memmove
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; CHECK: ret void
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}
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define void @memSetTest(i8* nocapture %x) {
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entry:
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tail call void @llvm.memset.p0i8.i64(i8* align 4 %x, i8 77, i64 16, i1 false)
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ret void
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; CHECK: define void @memSetTest
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; CHECK: call i8* @memset
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; CHECK: ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Ensure that esan doesn't convert element atomic memory intrinsics to
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; calls.
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declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture writeonly, i8, i64, i32) nounwind
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declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind
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declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind
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define void @elementAtomic_memCpyTest(i8* nocapture %x, i8* nocapture %y) {
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; CHECK-LABEL: elementAtomic_memCpyTest
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; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 1 %y, i64 16, i32 1)
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; CHECK-NEXT: ret void
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tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 1 %y, i64 16, i32 1)
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ret void
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}
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define void @elementAtomic_memMoveTest(i8* nocapture %x, i8* nocapture %y) {
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; CHECK-LABEL: elementAtomic_memMoveTest
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; CHECK-NEXT: tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 1 %y, i64 16, i32 1)
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; CHECK-NEXT: ret void
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tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 1 %y, i64 16, i32 1)
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ret void
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}
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define void @elementAtomic_memSetTest(i8* nocapture %x) {
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; CHECK-LABEL: elementAtomic_memSetTest
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; CHECK-NEXT: tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %x, i8 77, i64 16, i32 1)
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; CHECK-NEXT: ret void
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tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %x, i8 77, i64 16, i32 1)
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ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Top-level:
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; CHECK: define internal void @esan.module_ctor()
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; CHECK: call void @__esan_init(i32 2, i8* null)
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; CHECK: define internal void @esan.module_dtor()
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; CHECK: call void @__esan_exit(i8* null)
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