forked from OSchip/llvm-project
60 lines
2.0 KiB
LLVM
60 lines
2.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i16 0, align 2
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_llltus:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
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; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ult i16 %a, %b
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%conv3 = zext i1 %cmp to i64
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ret i64 %conv3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_llltus_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
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; CHECK-NEXT: sradi r3, [[REG]], 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ult i16 %a, %b
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%conv3 = sext i1 %cmp to i64
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ret i64 %conv3
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}
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; Function Attrs: norecurse nounwind
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define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_llltus_store:
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; CHECK: sub [[REG:r[2-9]+]], r3, r4
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; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
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entry:
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%cmp = icmp ult i16 %a, %b
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%conv3 = zext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: test_llltus_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK: sub [[REG:r[0-9]+]], r3, r4
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; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
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entry:
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%cmp = icmp ult i16 %a, %b
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%conv3 = sext i1 %cmp to i16
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store i16 %conv3, i16* @glob, align 2
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ret void
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}
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