forked from OSchip/llvm-project
78 lines
2.5 KiB
LLVM
78 lines
2.5 KiB
LLVM
; RUN: llc -march=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s
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@g0 = common global double 0.000000e+00, align 8
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@g1 = common global double 0.000000e+00, align 8
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; CHECK-LABEL: f0:
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; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo
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define double @f0(i32 %a0, i32 %a1) {
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b0:
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%v0 = load double, double* @g0, align 8, !tbaa !0
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%v1 = fptosi double %v0 to i64
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%v2 = load double, double* @g1, align 8, !tbaa !0
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%v3 = fptosi double %v2 to i64
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%v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a0)
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%v5 = sitofp i64 %v4 to double
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ret double %v5
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64, i64, i32) #0
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; CHECK-LABEL: f1:
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; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi
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define double @f1(i32 %a0, i32 %a1) {
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b0:
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%v0 = load double, double* @g0, align 8, !tbaa !0
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%v1 = fptosi double %v0 to i64
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%v2 = load double, double* @g1, align 8, !tbaa !0
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%v3 = fptosi double %v2 to i64
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%v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a1)
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%v5 = sitofp i64 %v4 to double
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ret double %v5
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}
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; CHECK-LABEL: f2:
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; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo
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define double @f2(i32 %a0, i32 %a1) {
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b0:
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%v0 = load double, double* @g1, align 8, !tbaa !0
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%v1 = fptosi double %v0 to i64
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%v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a0)
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%v3 = sitofp i64 %v2 to double
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ret double %v3
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.vrcmpys.s1(i64, i32) #0
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; CHECK-LABEL: f3:
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; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi
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define double @f3(i32 %a0, i32 %a1) {
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b0:
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%v0 = load double, double* @g1, align 8, !tbaa !0
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%v1 = fptosi double %v0 to i64
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%v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a1)
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%v3 = sitofp i64 %v2 to double
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ret double %v3
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}
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; CHECK-LABEL: f4:
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; CHECK: e9a4c2e0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:lo }
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; CHECK: e9a4c2c0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:hi }
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define void @f4() {
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b0:
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call void asm sideeffect "r0=vrcmpys(r5:4,r2):<<1:rnd:sat", ""(), !srcloc !4
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call void asm sideeffect "r0=vrcmpys(r5:4,r3):<<1:rnd:sat", ""(), !srcloc !5
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ret void
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}
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attributes #0 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"double", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{i32 25}
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!5 = !{i32 71}
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