forked from OSchip/llvm-project
121 lines
4.9 KiB
LLVM
121 lines
4.9 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; CHECK: vmem(r{{[0-9]+}}++#1)
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; CHECK: vmem(r{{[0-9]+}}++#1)
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; CHECK: vmem(r{{[0-9]+}}++#1)
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; CHECK: vmem(r{{[0-9]+}}++#1)
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @f0(i16* nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, i8* nocapture %a4, i32 %a5) #0 {
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b0:
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%v0 = ashr i32 %a3, 2
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%v1 = ashr i32 %a3, 1
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%v2 = add i32 %v1, %v0
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%v3 = icmp sgt i32 %a2, 0
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br i1 %v3, label %b1, label %b8
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b1: ; preds = %b0
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%v4 = sdiv i32 %a1, 64
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%v5 = icmp sgt i32 %a1, 63
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br label %b2
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b2: ; preds = %b6, %b1
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%v6 = phi i32 [ 0, %b1 ], [ %v56, %b6 ]
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%v7 = ashr exact i32 %v6, 1
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%v8 = mul nsw i32 %v7, %a3
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br i1 %v5, label %b3, label %b6
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b3: ; preds = %b2
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%v9 = add nsw i32 %v6, 1
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%v10 = mul nsw i32 %v9, %a5
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%v11 = mul nsw i32 %v6, %a5
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%v12 = add i32 %v2, %v8
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%v13 = add i32 %v8, %v0
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%v14 = add i32 %v8, %v1
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%v15 = getelementptr inbounds i8, i8* %a4, i32 %v10
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%v16 = getelementptr inbounds i8, i8* %a4, i32 %v11
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%v17 = getelementptr inbounds i16, i16* %a0, i32 %v12
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%v18 = getelementptr inbounds i16, i16* %a0, i32 %v13
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%v19 = getelementptr inbounds i16, i16* %a0, i32 %v14
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%v20 = getelementptr inbounds i16, i16* %a0, i32 %v8
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%v21 = bitcast i8* %v15 to <16 x i32>*
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%v22 = bitcast i8* %v16 to <16 x i32>*
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%v23 = bitcast i16* %v17 to <16 x i32>*
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%v24 = bitcast i16* %v18 to <16 x i32>*
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%v25 = bitcast i16* %v19 to <16 x i32>*
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%v26 = bitcast i16* %v20 to <16 x i32>*
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br label %b4
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b4: ; preds = %b4, %b3
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%v27 = phi i32 [ 0, %b3 ], [ %v54, %b4 ]
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%v28 = phi <16 x i32>* [ %v26, %b3 ], [ %v34, %b4 ]
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%v29 = phi <16 x i32>* [ %v25, %b3 ], [ %v36, %b4 ]
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%v30 = phi <16 x i32>* [ %v24, %b3 ], [ %v38, %b4 ]
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%v31 = phi <16 x i32>* [ %v23, %b3 ], [ %v40, %b4 ]
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%v32 = phi <16 x i32>* [ %v21, %b3 ], [ %v53, %b4 ]
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%v33 = phi <16 x i32>* [ %v22, %b3 ], [ %v52, %b4 ]
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%v34 = getelementptr inbounds <16 x i32>, <16 x i32>* %v28, i32 1
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%v35 = load <16 x i32>, <16 x i32>* %v28, align 64, !tbaa !0
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%v36 = getelementptr inbounds <16 x i32>, <16 x i32>* %v29, i32 1
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%v37 = load <16 x i32>, <16 x i32>* %v29, align 64, !tbaa !0
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%v38 = getelementptr inbounds <16 x i32>, <16 x i32>* %v30, i32 1
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%v39 = load <16 x i32>, <16 x i32>* %v30, align 64, !tbaa !0
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%v40 = getelementptr inbounds <16 x i32>, <16 x i32>* %v31, i32 1
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%v41 = load <16 x i32>, <16 x i32>* %v31, align 64, !tbaa !0
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%v42 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v35, <16 x i32> %v37)
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%v43 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v35, <16 x i32> %v37)
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%v44 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v39, <16 x i32> %v41)
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%v45 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v39, <16 x i32> %v41)
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%v46 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v42, <16 x i32> %v44)
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%v47 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v42, <16 x i32> %v44)
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%v48 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v43, <16 x i32> %v45)
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%v49 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v43, <16 x i32> %v45)
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%v50 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v47, <16 x i32> %v46)
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%v51 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v49, <16 x i32> %v48)
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%v52 = getelementptr inbounds <16 x i32>, <16 x i32>* %v33, i32 1
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store <16 x i32> %v50, <16 x i32>* %v33, align 64, !tbaa !0
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%v53 = getelementptr inbounds <16 x i32>, <16 x i32>* %v32, i32 1
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store <16 x i32> %v51, <16 x i32>* %v32, align 64, !tbaa !0
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%v54 = add nsw i32 %v27, 1
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%v55 = icmp slt i32 %v54, %v4
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br i1 %v55, label %b4, label %b5
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b5: ; preds = %b4
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br label %b6
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b6: ; preds = %b5, %b2
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%v56 = add nsw i32 %v6, 2
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%v57 = icmp slt i32 %v56, %a2
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br i1 %v57, label %b2, label %b7
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b7: ; preds = %b6
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br label %b8
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b8: ; preds = %b7, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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