forked from OSchip/llvm-project
67 lines
2.5 KiB
LLVM
67 lines
2.5 KiB
LLVM
; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s | FileCheck %s
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; Test that we generate the correct offsets after we removed unneeded
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; chain dependences between Phis and generated a better pipeline.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: = memd([[REG0:(r[0-9]+)]]+#8)
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; CHECK: memd([[REG0]]++#8) =
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; CHECK: }{{[ \t]*}}:endloop0
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@g0 = common global [400 x i8] zeroinitializer, align 8
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@g1 = common global [400 x i8] zeroinitializer, align 8
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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br label %b2
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b1: ; preds = %b2
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ret void
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b2: ; preds = %b2, %b0
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%v0 = phi i8* [ getelementptr inbounds ([400 x i8], [400 x i8]* @g0, i32 0, i32 0), %b0 ], [ %v23, %b2 ]
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%v1 = phi i8* [ getelementptr inbounds ([400 x i8], [400 x i8]* @g1, i32 0, i32 0), %b0 ], [ %v24, %b2 ]
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%v2 = phi i32 [ 0, %b0 ], [ %v21, %b2 ]
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%v3 = bitcast i8* %v0 to <8 x i8>*
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%v4 = load <8 x i8>, <8 x i8>* %v3, align 8
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%v5 = bitcast i8* %v1 to <8 x i8>*
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%v6 = load <8 x i8>, <8 x i8>* %v5, align 8
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%v7 = bitcast <8 x i8> %v4 to <2 x i32>
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%v8 = extractelement <2 x i32> %v7, i32 0
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%v9 = extractelement <2 x i32> %v7, i32 1
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%v10 = bitcast <8 x i8> %v6 to <2 x i32>
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%v11 = extractelement <2 x i32> %v10, i32 0
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%v12 = extractelement <2 x i32> %v10, i32 1
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%v13 = tail call i64 @llvm.hexagon.S2.vzxtbh(i32 %v11)
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%v14 = tail call i64 @llvm.hexagon.S2.vzxtbh(i32 %v12)
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%v15 = tail call i64 @llvm.hexagon.M5.vmacbsu(i64 %v13, i32 %v8, i32 117901063)
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%v16 = tail call i64 @llvm.hexagon.M5.vmacbsu(i64 %v14, i32 %v9, i32 117901063)
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%v17 = tail call i32 @llvm.hexagon.S2.vtrunehb(i64 %v15)
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%v18 = tail call i32 @llvm.hexagon.S2.vtrunehb(i64 %v16)
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%v19 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v18, i32 %v17)
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%v20 = bitcast i64 %v19 to <8 x i8>
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store <8 x i8> %v20, <8 x i8>* %v5, align 8
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%v21 = add nsw i32 %v2, 8
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%v22 = icmp slt i32 %v2, 392
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%v23 = getelementptr i8, i8* %v0, i32 8
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%v24 = getelementptr i8, i8* %v1, i32 8
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br i1 %v22, label %b2, label %b1
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.vzxtbh(i32) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M5.vmacbsu(i64, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.vtrunehb(i64) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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