forked from OSchip/llvm-project
264 lines
16 KiB
LLVM
264 lines
16 KiB
LLVM
; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; Test that the register scavenger does not assert because a spill slot
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; was not found. The bug is that the Hexagon spill code was not allocating
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; the spill slot because the function that returns true, which indicates
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; the code changed when a spill is inserted, was not always returning true.
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; Function Attrs: nounwind
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define void @f0(i8* noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, i8* noalias nocapture %a4, i32 %a5) #0 {
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b0:
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%v0 = sub i32 0, %a1
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%v1 = getelementptr inbounds i8, i8* %a0, i32 %v0
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%v2 = getelementptr inbounds i8, i8* %a0, i32 %a1
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%v3 = mul nsw i32 %a1, 2
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%v4 = getelementptr inbounds i8, i8* %a0, i32 %v3
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%v5 = bitcast i8* %a4 to <16 x i32>*
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%v6 = getelementptr inbounds i8, i8* %a4, i32 %a5
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%v7 = bitcast i8* %v6 to <16 x i32>*
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%v8 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
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%v9 = load <16 x i32>, <16 x i32>* undef, align 64
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%v10 = or i64 undef, 0
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%v11 = trunc i64 %v10 to i32
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%v12 = load i8, i8* undef, align 1
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%v13 = zext i8 %v12 to i64
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%v14 = shl nuw nsw i64 %v13, 8
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%v15 = or i64 0, %v14
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%v16 = trunc i64 %v15 to i32
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%v17 = load i8, i8* undef, align 1
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%v18 = zext i8 %v17 to i64
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%v19 = or i64 0, %v18
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%v20 = or i64 %v19, 0
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%v21 = or i64 %v20, 0
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%v22 = trunc i64 %v21 to i32
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%v23 = load i8, i8* undef, align 1
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%v24 = zext i8 %v23 to i64
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%v25 = shl nuw nsw i64 %v24, 8
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%v26 = or i64 undef, %v25
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%v27 = trunc i64 %v26 to i32
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%v28 = icmp sgt i32 %a2, 64
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br i1 %v28, label %b1, label %b6
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b1: ; preds = %b0
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%v29 = getelementptr inbounds i8, i8* %v4, i32 64
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%v30 = bitcast i8* %v29 to <16 x i32>*
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%v31 = getelementptr inbounds i8, i8* %v2, i32 64
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%v32 = bitcast i8* %v31 to <16 x i32>*
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%v33 = getelementptr inbounds i8, i8* %a0, i32 64
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%v34 = bitcast i8* %v33 to <16 x i32>*
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%v35 = getelementptr inbounds i8, i8* %v1, i32 64
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%v36 = bitcast i8* %v35 to <16 x i32>*
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%v37 = add i32 0, 64
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%v38 = getelementptr i8, i8* %a4, i32 %v37
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%v39 = add i32 %a2, -65
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%v40 = lshr i32 %v39, 6
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%v41 = add nuw nsw i32 %v40, 1
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%v42 = and i32 %v41, 3
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%v43 = icmp eq i32 %v42, 0
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br i1 undef, label %b2, label %b4
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b2: ; preds = %b2, %b1
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%v44 = phi i32 [ %v144, %b2 ], [ %a2, %b1 ]
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%v45 = phi <16 x i32> [ %v101, %b2 ], [ %v8, %b1 ]
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%v46 = phi <16 x i32> [ %v113, %b2 ], [ undef, %b1 ]
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%v47 = phi <16 x i32> [ %v102, %b2 ], [ %v8, %b1 ]
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%v48 = phi <16 x i32> [ %v118, %b2 ], [ undef, %b1 ]
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%v49 = phi <16 x i32>* [ %v112, %b2 ], [ %v36, %b1 ]
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%v50 = phi <16 x i32>* [ %v114, %b2 ], [ %v34, %b1 ]
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%v51 = phi <16 x i32>* [ %v116, %b2 ], [ %v32, %b1 ]
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%v52 = phi <16 x i32>* [ undef, %b2 ], [ %v30, %b1 ]
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%v53 = phi <16 x i32>* [ %v139, %b2 ], [ %v5, %b1 ]
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%v54 = phi <16 x i32>* [ %v143, %b2 ], [ %v7, %b1 ]
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%v55 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v46, <16 x i32> %v45, i32 1)
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%v56 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> undef, <16 x i32> %v47, i32 1)
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%v57 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 1
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%v58 = load <16 x i32>, <16 x i32>* %v49, align 64
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%v59 = getelementptr inbounds <16 x i32>, <16 x i32>* %v50, i32 1
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%v60 = load <16 x i32>, <16 x i32>* %v50, align 64
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%v61 = load <16 x i32>, <16 x i32>* %v51, align 64
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%v62 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v58, <16 x i32> %v46, i32 1)
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%v63 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v60, <16 x i32> undef, i32 1)
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%v64 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v61, <16 x i32> undef, i32 1)
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%v65 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> undef, <16 x i32> %v48, i32 1)
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%v66 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v62, <16 x i32> %v55)
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%v67 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v63, <16 x i32> %v56)
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%v68 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v66, i32 %v11)
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%v69 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> undef)
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%v70 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v68, <32 x i32> %v67, i32 %v16)
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%v71 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v62, <16 x i32> %v63)
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%v72 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v70, <32 x i32> %v71, i32 %v22)
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%v73 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v72, <32 x i32> %v69, i32 0)
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%v74 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v73, <16 x i32> %v64, i32 %v27)
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%v75 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> zeroinitializer, <16 x i32> %v65, i32 %v27)
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%v76 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v74)
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%v77 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v76, <16 x i32> undef, i32 %a3)
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%v78 = getelementptr inbounds <16 x i32>, <16 x i32>* %v53, i32 1
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store <16 x i32> %v77, <16 x i32>* %v53, align 64
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%v79 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v75)
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%v80 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v79, <16 x i32> undef, i32 %a3)
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%v81 = getelementptr inbounds <16 x i32>, <16 x i32>* %v54, i32 1
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store <16 x i32> %v80, <16 x i32>* %v54, align 64
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%v82 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 2
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%v83 = load <16 x i32>, <16 x i32>* %v57, align 64
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%v84 = getelementptr inbounds <16 x i32>, <16 x i32>* %v50, i32 2
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%v85 = load <16 x i32>, <16 x i32>* %v59, align 64
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%v86 = load <16 x i32>, <16 x i32>* undef, align 64
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%v87 = load <16 x i32>, <16 x i32>* null, align 64
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%v88 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v83, <16 x i32> %v58, i32 1)
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%v89 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v85, <16 x i32> %v60, i32 1)
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%v90 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v86, <16 x i32> %v61, i32 1)
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%v91 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v90, <16 x i32> undef)
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%v92 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> undef, <32 x i32> undef, i32 %v16)
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%v93 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v88, <16 x i32> %v89)
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%v94 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v92, <32 x i32> %v93, i32 %v22)
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%v95 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v94, <32 x i32> %v91, i32 0)
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%v96 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v95, <16 x i32> %v90, i32 %v27)
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%v97 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v96)
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%v98 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v97, <16 x i32> undef, i32 %a3)
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store <16 x i32> %v98, <16 x i32>* %v78, align 64
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%v99 = getelementptr inbounds <16 x i32>, <16 x i32>* %v54, i32 2
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store <16 x i32> undef, <16 x i32>* %v81, align 64
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%v100 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 3
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%v101 = load <16 x i32>, <16 x i32>* %v82, align 64
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%v102 = load <16 x i32>, <16 x i32>* %v84, align 64
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%v103 = getelementptr inbounds <16 x i32>, <16 x i32>* %v51, i32 3
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%v104 = load <16 x i32>, <16 x i32>* null, align 64
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%v105 = getelementptr inbounds <16 x i32>, <16 x i32>* %v52, i32 3
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%v106 = load <16 x i32>, <16 x i32>* undef, align 64
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%v107 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> undef, i32 %a3)
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store <16 x i32> %v107, <16 x i32>* undef, align 64
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%v108 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> undef, i32 %a3)
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%v109 = getelementptr inbounds <16 x i32>, <16 x i32>* %v54, i32 3
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store <16 x i32> %v108, <16 x i32>* %v99, align 64
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%v110 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v104, <16 x i32> %v86, i32 1)
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%v111 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v106, <16 x i32> %v87, i32 1)
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%v112 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 4
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%v113 = load <16 x i32>, <16 x i32>* %v100, align 64
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%v114 = getelementptr inbounds <16 x i32>, <16 x i32>* %v50, i32 4
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%v115 = load <16 x i32>, <16 x i32>* undef, align 64
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%v116 = getelementptr inbounds <16 x i32>, <16 x i32>* %v51, i32 4
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%v117 = load <16 x i32>, <16 x i32>* %v103, align 64
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%v118 = load <16 x i32>, <16 x i32>* %v105, align 64
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%v119 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v113, <16 x i32> %v101, i32 1)
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%v120 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v115, <16 x i32> %v102, i32 1)
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%v121 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v117, <16 x i32> %v104, i32 1)
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%v122 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v118, <16 x i32> %v106, i32 1)
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%v123 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v119, <16 x i32> undef)
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%v124 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v120, <16 x i32> undef)
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%v125 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v123, i32 %v11)
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%v126 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v124, i32 %v11)
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%v127 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v121, <16 x i32> %v110)
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%v128 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v125, <32 x i32> %v124, i32 %v16)
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%v129 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v126, <32 x i32> %v127, i32 %v16)
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%v130 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v128, <32 x i32> undef, i32 %v22)
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%v131 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v129, <32 x i32> undef, i32 %v22)
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%v132 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v122, <16 x i32> %v111)
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%v133 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v130, <32 x i32> %v127, i32 0)
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%v134 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v131, <32 x i32> %v132, i32 0)
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%v135 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v133, <16 x i32> %v121, i32 %v27)
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%v136 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v134, <16 x i32> %v122, i32 %v27)
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%v137 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v135)
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%v138 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v137, <16 x i32> undef, i32 %a3)
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%v139 = getelementptr inbounds <16 x i32>, <16 x i32>* %v53, i32 4
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store <16 x i32> %v138, <16 x i32>* undef, align 64
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%v140 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v136)
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%v141 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v136)
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%v142 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v140, <16 x i32> %v141, i32 %a3)
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%v143 = getelementptr inbounds <16 x i32>, <16 x i32>* %v54, i32 4
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store <16 x i32> %v142, <16 x i32>* %v109, align 64
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%v144 = add nsw i32 %v44, -256
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%v145 = icmp sgt i32 %v144, 256
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br i1 %v145, label %b2, label %b3
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b3: ; preds = %b2
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%v146 = phi <16 x i32>* [ %v116, %b2 ]
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%v147 = phi <16 x i32>* [ %v114, %b2 ]
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%v148 = phi <16 x i32>* [ %v112, %b2 ]
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br i1 %v43, label %b5, label %b4
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b4: ; preds = %b3, %b1
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%v149 = phi <16 x i32> [ %v9, %b1 ], [ undef, %b3 ]
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%v150 = phi <16 x i32>* [ %v36, %b1 ], [ %v148, %b3 ]
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%v151 = phi <16 x i32>* [ %v34, %b1 ], [ %v147, %b3 ]
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%v152 = phi <16 x i32>* [ %v32, %b1 ], [ %v146, %b3 ]
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%v153 = phi <16 x i32>* [ %v5, %b1 ], [ undef, %b3 ]
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%v154 = load <16 x i32>, <16 x i32>* %v150, align 64
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%v155 = load <16 x i32>, <16 x i32>* %v151, align 64
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%v156 = load <16 x i32>, <16 x i32>* %v152, align 64
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%v157 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v154, <16 x i32> undef, i32 1)
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%v158 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v155, <16 x i32> undef, i32 1)
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%v159 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v156, <16 x i32> %v149, i32 1)
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%v160 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v157, <16 x i32> %v158)
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%v161 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v160, i32 %v22)
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%v162 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v161, <32 x i32> undef, i32 0)
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%v163 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v162, <16 x i32> %v159, i32 %v27)
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%v164 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v163)
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%v165 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v164, <16 x i32> undef, i32 %a3)
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store <16 x i32> %v165, <16 x i32>* %v153, align 64
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unreachable
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b5: ; preds = %b3
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%v166 = bitcast i8* %v38 to <16 x i32>*
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br label %b6
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b6: ; preds = %b5, %b0
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%v167 = phi <16 x i32> [ %v8, %b0 ], [ undef, %b5 ]
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%v168 = phi <16 x i32>* [ %v5, %b0 ], [ %v166, %b5 ]
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%v169 = phi <16 x i32>* [ %v7, %b0 ], [ undef, %b5 ]
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%v170 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> undef, <16 x i32> %v167, i32 1)
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%v171 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> undef, <16 x i32> undef, i32 1)
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%v172 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v170)
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%v173 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v171)
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%v174 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v171, <16 x i32> undef)
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%v175 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v173, i32 %v22)
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%v176 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v174, i32 %v22)
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%v177 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v175, <32 x i32> %v172, i32 0)
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%v178 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v176, <32 x i32> undef, i32 0)
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%v179 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v177, <16 x i32> undef, i32 %v27)
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%v180 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v178, <16 x i32> undef, i32 %v27)
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%v181 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v179)
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%v182 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v181, i32 %a3)
|
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store <16 x i32> %v182, <16 x i32>* %v168, align 64
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%v183 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v180)
|
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%v184 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v183, i32 %a3)
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store <16 x i32> %v184, <16 x i32>* %v169, align 64
|
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ret void
|
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vd0() #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32>, i32) #1
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; Function Attrs: nounwind readnone
|
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declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #1
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; Function Attrs: nounwind readnone
|
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declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #1
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; Function Attrs: nounwind readnone
|
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declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
|
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declare <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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|
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attributes #0 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" }
|
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attributes #1 = { nounwind readnone }
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