forked from OSchip/llvm-project
61 lines
2.6 KiB
LLVM
61 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
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; CHECK-LABEL: name: test_f32_inreg
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; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY $sgpr0
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]]
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define amdgpu_vs void @test_f32_inreg(float inreg %arg0) {
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call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
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ret void
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}
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; CHECK-LABEL: name: test_f32
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; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]]
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define amdgpu_vs void @test_f32(float %arg0) {
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call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
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ret void
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}
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; CHECK-LABEL: name: test_ptr2_byval
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; CHECK: [[S01:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
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; CHECK: G_LOAD [[S01]]
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define amdgpu_vs void @test_ptr2_byval(i32 addrspace(4)* byval %arg0) {
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%tmp0 = load volatile i32, i32 addrspace(4)* %arg0
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ret void
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}
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; CHECK-LABEL: name: test_ptr2_inreg
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; CHECK: [[S01:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
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; CHECK: G_LOAD [[S01]]
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define amdgpu_vs void @test_ptr2_inreg(i32 addrspace(4)* inreg %arg0) {
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%tmp0 = load volatile i32, i32 addrspace(4)* %arg0
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ret void
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}
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; CHECK-LABEL: name: test_sgpr_alignment0
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; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY $sgpr0
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; CHECK: [[S23:%[0-9]+]]:_(p4) = COPY $sgpr2_sgpr3
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; CHECK: G_LOAD [[S23]]
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]]
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define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, i32 addrspace(4)* inreg %arg1) {
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%tmp0 = load volatile i32, i32 addrspace(4)* %arg1
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call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
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ret void
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}
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; CHECK-LABEL: name: test_order
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; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY $sgpr0
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; CHECK: [[S1:%[0-9]+]]:_(s32) = COPY $sgpr1
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; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[V1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]](s32), [[S0]](s32), [[V1]](s32), [[S1]](s32)
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define amdgpu_vs void @test_order(float inreg %arg0, float inreg %arg1, float %arg2, float %arg3) {
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call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg2, float %arg0, float %arg3, float %arg1, i1 false, i1 false) #0
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ret void
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}
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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attributes #0 = { nounwind }
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