forked from OSchip/llvm-project
155 lines
3.7 KiB
LLVM
155 lines
3.7 KiB
LLVM
; Testg 64-bit signed division and remainder.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Testg register division. The result is in the second of the two registers.
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define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
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; CHECK: f1:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgr %r2, %r4
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; CHECK: stg %r3, 0(%r5)
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; CHECK: br %r14
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%div = sdiv i64 %a, %b
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store i64 %div, i64 *%dest
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ret void
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}
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; Testg register remainder. The result is in the first of the two registers.
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define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
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; CHECK: f2:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgr %r2, %r4
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; CHECK: stg %r2, 0(%r5)
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; CHECK: br %r14
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%rem = srem i64 %a, %b
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store i64 %rem, i64 *%dest
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ret void
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}
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; Testg that division and remainder use a single instruction.
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define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
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; CHECK: f3:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgr %r2, %r4
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; CHECK-NOT: dsgr
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; CHECK: ogr %r2, %r3
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; CHECK: br %r14
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%div = sdiv i64 %a, %b
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%rem = srem i64 %a, %b
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%or = or i64 %rem, %div
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ret i64 %or
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}
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; Testg memory division with no displacement.
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define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
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; CHECK: f4:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsg %r2, 0(%r4)
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; CHECK: stg %r3, 0(%r5)
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; CHECK: br %r14
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%b = load i64 *%src
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%div = sdiv i64 %a, %b
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store i64 %div, i64 *%dest
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ret void
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}
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; Testg memory remainder with no displacement.
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define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
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; CHECK: f5:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsg %r2, 0(%r4)
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; CHECK: stg %r2, 0(%r5)
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; CHECK: br %r14
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%b = load i64 *%src
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%rem = srem i64 %a, %b
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store i64 %rem, i64 *%dest
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ret void
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}
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; Testg both memory division and memory remainder.
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define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK: f6:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsg %r2, 0(%r4)
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; CHECK-NOT: {{dsg|dsgr}}
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; CHECK: ogr %r2, %r3
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; CHECK: br %r14
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%b = load i64 *%src
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%div = sdiv i64 %a, %b
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%rem = srem i64 %a, %b
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%or = or i64 %rem, %div
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ret i64 %or
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}
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; Check the high end of the DSG range.
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define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK: f7:
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; CHECK: dsg %r2, 524280(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65535
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%b = load i64 *%ptr
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK: f8:
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; CHECK: agfi %r4, 524288
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; CHECK: dsg %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65536
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%b = load i64 *%ptr
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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; Check the high end of the negative aligned DSG range.
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define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK: f9:
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; CHECK: dsg %r2, -8(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -1
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%b = load i64 *%ptr
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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; Check the low end of the DSG range.
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define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK: f10:
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; CHECK: dsg %r2, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65536
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%b = load i64 *%ptr
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK: f11:
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; CHECK: agfi %r4, -524296
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; CHECK: dsg %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65537
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%b = load i64 *%ptr
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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; Check that DSG allows an index.
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define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
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; CHECK: f12:
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; CHECK: dsg %r2, 524287(%r5,%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%b = load i64 *%ptr
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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