forked from OSchip/llvm-project
115 lines
2.5 KiB
LLVM
115 lines
2.5 KiB
LLVM
; Test zero extensions from a halfword to an i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test register extension, starting with an i32.
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define i32 @f1(i32 %a) {
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; CHECK: f1:
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; CHECK: llhr %r2, %r2
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; CHECk: br %r14
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%half = trunc i32 %a to i16
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; ...and again with an i64.
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define i32 @f2(i64 %a) {
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; CHECK: f2:
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; CHECK: llhr %r2, %r2
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; CHECk: br %r14
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%half = trunc i64 %a to i16
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check ANDs that are equivalent to zero extension.
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define i32 @f3(i32 %a) {
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; CHECK: f3:
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; CHECK: llhr %r2, %r2
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; CHECk: br %r14
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%ext = and i32 %a, 65535
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ret i32 %ext
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}
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; Check LLH with no displacement.
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define i32 @f4(i16 *%src) {
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; CHECK: f4:
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; CHECK: llh %r2, 0(%r2)
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; CHECK: br %r14
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%half = load i16 *%src
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the high end of the LLH range.
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define i32 @f5(i16 *%src) {
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; CHECK: f5:
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; CHECK: llh %r2, 524286(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16 *%src, i64 262143
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%half = load i16 *%ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f6(i16 *%src) {
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; CHECK: f6:
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; CHECK: agfi %r2, 524288
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; CHECK: llh %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16 *%src, i64 262144
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%half = load i16 *%ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the high end of the negative LLH range.
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define i32 @f7(i16 *%src) {
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; CHECK: f7:
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; CHECK: llh %r2, -2(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16 *%src, i64 -1
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%half = load i16 *%ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the low end of the LLH range.
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define i32 @f8(i16 *%src) {
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; CHECK: f8:
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; CHECK: llh %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16 *%src, i64 -262144
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%half = load i16 *%ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the next halfword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f9(i16 *%src) {
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; CHECK: f9:
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; CHECK: agfi %r2, -524290
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; CHECK: llh %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16 *%src, i64 -262145
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%half = load i16 *%ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check that LLH allows an index
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define i32 @f10(i64 %src, i64 %index) {
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; CHECK: f10:
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; CHECK: llh %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i16 *
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%half = load i16 *%ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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