llvm-project

History

Nicolai Haehnle 41abf2766e AMDGPU: Prepare for explicit absolute relocations in code generation Summary: We will use absolute relocations for LDS symbols. Change-Id: I9a32795ed0ea835e433a787129cfe3c57ee9a325 Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61492 llvm-svn: 363517		2019-06-16 17:43:37 +00:00
..
AArch64	[MIR-Canon] Skip the first N vreg names lazily.	2019-05-31 06:02:38 +00:00
AMDGPU	AMDGPU: Prepare for explicit absolute relocations in code generation	2019-06-16 17:43:37 +00:00
ARM	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Generic	[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL	2018-10-01 21:59:45 +00:00
Hexagon	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Mips	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
NVPTX	[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.	2018-01-10 00:56:48 +00:00
PowerPC	[Power9] Allow gpr callee saved spills in prologue to vectors registers	2018-11-09 16:36:24 +00:00
WebAssembly	[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)	2018-05-08 02:02:50 +00:00
X86	[llvm-readobj] Change -long-option to --long-option in tests. NFC	2019-05-01 05:27:20 +00:00
README	…

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.