forked from OSchip/llvm-project
324 lines
9.9 KiB
C++
324 lines
9.9 KiB
C++
//===- MipsOptimizePICCall.cpp - Optimize PIC Calls -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass eliminates unnecessary instructions that set up $gp and replace
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// instructions that load target function addresses with copy instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/ADT/ScopedHashTable.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/Support/Allocator.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/RecyclingAllocator.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOpcodes.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <cassert>
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#include <utility>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "optimize-mips-pic-call"
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static cl::opt<bool> LoadTargetFromGOT("mips-load-target-from-got",
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cl::init(true),
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cl::desc("Load target address from GOT"),
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cl::Hidden);
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static cl::opt<bool> EraseGPOpnd("mips-erase-gp-opnd",
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cl::init(true), cl::desc("Erase GP Operand"),
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cl::Hidden);
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namespace {
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using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>;
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using CntRegP = std::pair<unsigned, unsigned>;
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using AllocatorTy = RecyclingAllocator<BumpPtrAllocator,
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ScopedHashTableVal<ValueType, CntRegP>>;
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using ScopedHTType = ScopedHashTable<ValueType, CntRegP,
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DenseMapInfo<ValueType>, AllocatorTy>;
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class MBBInfo {
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public:
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MBBInfo(MachineDomTreeNode *N);
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const MachineDomTreeNode *getNode() const;
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bool isVisited() const;
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void preVisit(ScopedHTType &ScopedHT);
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void postVisit();
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private:
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MachineDomTreeNode *Node;
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ScopedHTType::ScopeTy *HTScope;
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};
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class OptimizePICCall : public MachineFunctionPass {
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public:
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OptimizePICCall() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return "Mips OptimizePICCall"; }
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bool runOnMachineFunction(MachineFunction &F) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// \brief Visit MBB.
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bool visitNode(MBBInfo &MBBI);
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/// \brief Test if MI jumps to a function via a register.
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///
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/// Also, return the virtual register containing the target function's address
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/// and the underlying object in Reg and Val respectively, if the function's
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/// address can be resolved lazily.
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bool isCallViaRegister(MachineInstr &MI, unsigned &Reg,
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ValueType &Val) const;
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/// \brief Return the number of instructions that dominate the current
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/// instruction and load the function address from object Entry.
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unsigned getCount(ValueType Entry);
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/// \brief Return the destination virtual register of the last instruction
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/// that loads from object Entry.
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unsigned getReg(ValueType Entry);
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/// \brief Update ScopedHT.
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void incCntAndSetReg(ValueType Entry, unsigned Reg);
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ScopedHTType ScopedHT;
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static char ID;
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};
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} // end of anonymous namespace
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char OptimizePICCall::ID = 0;
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/// Return the first MachineOperand of MI if it is a used virtual register.
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static MachineOperand *getCallTargetRegOpnd(MachineInstr &MI) {
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if (MI.getNumOperands() == 0)
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return nullptr;
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MachineOperand &MO = MI.getOperand(0);
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if (!MO.isReg() || !MO.isUse() ||
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!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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return nullptr;
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return &MO;
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}
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/// Return type of register Reg.
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static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) {
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
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assert(TRI.legalclasstypes_end(*RC) - TRI.legalclasstypes_begin(*RC) == 1);
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return *TRI.legalclasstypes_begin(*RC);
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}
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/// Do the following transformation:
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///
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/// jalr $vreg
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/// =>
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/// copy $t9, $vreg
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/// jalr $t9
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static void setCallTargetReg(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I) {
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MachineFunction &MF = *MBB->getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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unsigned SrcReg = I->getOperand(0).getReg();
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unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
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BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
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.addReg(SrcReg);
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I->getOperand(0).setReg(DstReg);
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}
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/// Search MI's operands for register GP and erase it.
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static void eraseGPOpnd(MachineInstr &MI) {
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if (!EraseGPOpnd)
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return;
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MachineFunction &MF = *MI.getParent()->getParent();
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MVT::SimpleValueType Ty = getRegTy(MI.getOperand(0).getReg(), MF);
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unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64;
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for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
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MachineOperand &MO = MI.getOperand(I);
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if (MO.isReg() && MO.getReg() == Reg) {
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MI.RemoveOperand(I);
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return;
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}
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}
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llvm_unreachable(nullptr);
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}
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MBBInfo::MBBInfo(MachineDomTreeNode *N) : Node(N), HTScope(nullptr) {}
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const MachineDomTreeNode *MBBInfo::getNode() const { return Node; }
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bool MBBInfo::isVisited() const { return HTScope; }
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void MBBInfo::preVisit(ScopedHTType &ScopedHT) {
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HTScope = new ScopedHTType::ScopeTy(ScopedHT);
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}
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void MBBInfo::postVisit() {
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delete HTScope;
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}
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// OptimizePICCall methods.
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bool OptimizePICCall::runOnMachineFunction(MachineFunction &F) {
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if (static_cast<const MipsSubtarget &>(F.getSubtarget()).inMips16Mode())
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return false;
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// Do a pre-order traversal of the dominator tree.
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MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
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bool Changed = false;
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SmallVector<MBBInfo, 8> WorkList(1, MBBInfo(MDT->getRootNode()));
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while (!WorkList.empty()) {
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MBBInfo &MBBI = WorkList.back();
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// If this MBB has already been visited, destroy the scope for the MBB and
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// pop it from the work list.
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if (MBBI.isVisited()) {
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MBBI.postVisit();
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WorkList.pop_back();
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continue;
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}
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// Visit the MBB and add its children to the work list.
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MBBI.preVisit(ScopedHT);
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Changed |= visitNode(MBBI);
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const MachineDomTreeNode *Node = MBBI.getNode();
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const std::vector<MachineDomTreeNode *> &Children = Node->getChildren();
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WorkList.append(Children.begin(), Children.end());
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}
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return Changed;
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}
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bool OptimizePICCall::visitNode(MBBInfo &MBBI) {
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bool Changed = false;
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MachineBasicBlock *MBB = MBBI.getNode()->getBlock();
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
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++I) {
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unsigned Reg;
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ValueType Entry;
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// Skip instructions that are not call instructions via registers.
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if (!isCallViaRegister(*I, Reg, Entry))
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continue;
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Changed = true;
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unsigned N = getCount(Entry);
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if (N != 0) {
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// If a function has been called more than twice, we do not have to emit a
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// load instruction to get the function address from the GOT, but can
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// instead reuse the address that has been loaded before.
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if (N >= 2 && !LoadTargetFromGOT)
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getCallTargetRegOpnd(*I)->setReg(getReg(Entry));
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// Erase the $gp operand if this isn't the first time a function has
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// been called. $gp needs to be set up only if the function call can go
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// through a lazy binding stub.
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eraseGPOpnd(*I);
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}
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if (Entry)
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incCntAndSetReg(Entry, Reg);
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setCallTargetReg(MBB, I);
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}
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return Changed;
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}
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bool OptimizePICCall::isCallViaRegister(MachineInstr &MI, unsigned &Reg,
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ValueType &Val) const {
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if (!MI.isCall())
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return false;
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MachineOperand *MO = getCallTargetRegOpnd(MI);
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// Return if MI is not a function call via a register.
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if (!MO)
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return false;
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// Get the instruction that loads the function address from the GOT.
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Reg = MO->getReg();
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Val = nullptr;
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MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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MachineInstr *DefMI = MRI.getVRegDef(Reg);
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assert(DefMI);
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// See if DefMI is an instruction that loads from a GOT entry that holds the
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// address of a lazy binding stub.
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if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3)
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return true;
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unsigned Flags = DefMI->getOperand(2).getTargetFlags();
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if (Flags != MipsII::MO_GOT_CALL && Flags != MipsII::MO_CALL_LO16)
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return true;
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// Return the underlying object for the GOT entry in Val.
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assert(DefMI->hasOneMemOperand());
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Val = (*DefMI->memoperands_begin())->getValue();
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if (!Val)
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Val = (*DefMI->memoperands_begin())->getPseudoValue();
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return true;
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}
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unsigned OptimizePICCall::getCount(ValueType Entry) {
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return ScopedHT.lookup(Entry).first;
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}
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unsigned OptimizePICCall::getReg(ValueType Entry) {
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unsigned Reg = ScopedHT.lookup(Entry).second;
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assert(Reg);
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return Reg;
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}
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void OptimizePICCall::incCntAndSetReg(ValueType Entry, unsigned Reg) {
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CntRegP P = ScopedHT.lookup(Entry);
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ScopedHT.insert(Entry, std::make_pair(P.first + 1, Reg));
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}
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/// Return an OptimizeCall object.
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FunctionPass *llvm::createMipsOptimizePICCallPass() {
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return new OptimizePICCall();
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}
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