forked from OSchip/llvm-project
420 lines
12 KiB
YAML
420 lines
12 KiB
YAML
# RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s
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--- |
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define void @test0() { ret void }
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define void @test1() { ret void }
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define void @test2() { ret void }
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define void @test3() { ret void }
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define void @test4() { ret void }
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define void @test5() { ret void }
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define void @loop0() { ret void }
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define void @loop1() { ret void }
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define void @loop2() { ret void }
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...
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---
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# Combined use/def transfer check, the basics.
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# CHECK-LABEL: name: test0
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# CHECK: S_NOP 0, implicit-def %0
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# CHECK: S_NOP 0, implicit-def %1
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# CHECK: S_NOP 0, implicit-def dead %2
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# CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %3.sub0
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# CHECK: S_NOP 0, implicit %3.sub1
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# CHECK: S_NOP 0, implicit undef %3.sub2
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# CHECK: %4 = COPY %3.sub0_sub1
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# CHECK: %5 = COPY undef %3.sub2_sub3
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# CHECK: S_NOP 0, implicit %4.sub0
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# CHECK: S_NOP 0, implicit %4.sub1
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# CHECK: S_NOP 0, implicit undef %5.sub0
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name: test0
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registers:
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- { id: 0, class: sreg_32 }
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- { id: 1, class: sreg_32 }
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- { id: 2, class: sreg_32 }
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- { id: 3, class: sreg_128 }
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- { id: 4, class: sreg_64 }
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- { id: 5, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def %0
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S_NOP 0, implicit-def %1
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S_NOP 0, implicit-def %2
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%3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
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S_NOP 0, implicit %3.sub0
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S_NOP 0, implicit %3.sub1
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S_NOP 0, implicit %3.sub2
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%4 = COPY %3.sub0_sub1
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%5 = COPY %3.sub2_sub3
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S_NOP 0, implicit %4.sub0
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S_NOP 0, implicit %4.sub1
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S_NOP 0, implicit %5.sub0
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...
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---
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# Check defined lanes transfer; Includes checking for some special cases like
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# undef operands or IMPLICIT_DEF definitions.
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# CHECK-LABEL: name: test1
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# CHECK: %0 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
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# CHECK: %1 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
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# CHECK: %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %1.sub0
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# CHECK: S_NOP 0, implicit undef %1.sub1
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# CHECK: S_NOP 0, implicit %1.sub2
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# CHECK: S_NOP 0, implicit %1.sub3
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# CHECK: S_NOP 0, implicit %2.sub0
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# CHECK: S_NOP 0, implicit undef %2.sub1
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# CHECK: %3 = IMPLICIT_DEF
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# CHECK: %4 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit undef %4.sub0
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# CHECK: S_NOP 0, implicit undef %4.sub1
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# CHECK: S_NOP 0, implicit %4.sub2
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# CHECK: S_NOP 0, implicit undef %4.sub3
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# CHECK: %5 = EXTRACT_SUBREG %0, {{[0-9]+}}
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# CHECK: %6 = EXTRACT_SUBREG %5, {{[0-9]+}}
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# CHECK: %7 = EXTRACT_SUBREG %5, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %5
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# CHECK: S_NOP 0, implicit %6
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# CHECK: S_NOP 0, implicit undef %7
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# CHECK: %8 = IMPLICIT_DEF
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# CHECK: %9 = EXTRACT_SUBREG undef %8, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit undef %9
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# CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit undef %10
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name: test1
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registers:
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- { id: 0, class: sreg_128 }
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- { id: 1, class: sreg_128 }
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- { id: 2, class: sreg_64 }
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- { id: 3, class: sreg_32 }
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- { id: 4, class: sreg_128 }
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- { id: 5, class: sreg_64 }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_64 }
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- { id: 9, class: sreg_32 }
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- { id: 10, class: sreg_128 }
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body: |
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bb.0:
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%0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2
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%1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
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%2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, %subreg.sub0
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S_NOP 0, implicit %1.sub0
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S_NOP 0, implicit %1.sub1
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S_NOP 0, implicit %1.sub2
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S_NOP 0, implicit %1.sub3
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S_NOP 0, implicit %2.sub0
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S_NOP 0, implicit %2.sub1
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%3 = IMPLICIT_DEF
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%4 = INSERT_SUBREG %0, %3, %subreg.sub0
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S_NOP 0, implicit %4.sub0
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S_NOP 0, implicit %4.sub1
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S_NOP 0, implicit %4.sub2
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S_NOP 0, implicit %4.sub3
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%5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
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%6 = EXTRACT_SUBREG %5, %subreg.sub0
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%7 = EXTRACT_SUBREG %5, %subreg.sub1
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S_NOP 0, implicit %5
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S_NOP 0, implicit %6
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S_NOP 0, implicit %7
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%8 = IMPLICIT_DEF
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%9 = EXTRACT_SUBREG %8, %subreg.sub1
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S_NOP 0, implicit %9
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%10 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
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S_NOP 0, implicit %10
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...
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---
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# Check used lanes transfer; Includes checking for some special cases like
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# undef operands.
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# CHECK-LABEL: name: test2
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# CHECK: S_NOP 0, implicit-def dead %0
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# CHECK: S_NOP 0, implicit-def %1
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# CHECK: S_NOP 0, implicit-def %2
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# CHECK: %3 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %3.sub1
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# CHECK: S_NOP 0, implicit %3.sub3
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# CHECK: S_NOP 0, implicit-def %4
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# CHECK: S_NOP 0, implicit-def dead %5
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# CHECK: %6 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %6
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# CHECK: S_NOP 0, implicit-def dead %7
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# CHECK: S_NOP 0, implicit-def %8
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# CHECK: %9 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %9.sub2
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# CHECK: S_NOP 0, implicit-def %10
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# CHECK: S_NOP 0, implicit-def dead %11
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# CHECK: %12 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %12.sub3
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# CHECK: S_NOP 0, implicit-def %13
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# CHECK: S_NOP 0, implicit-def dead %14
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# CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
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# CHECK: %16 = EXTRACT_SUBREG %15, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %16.sub1
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name: test2
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registers:
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- { id: 0, class: sreg_32 }
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- { id: 1, class: sreg_32 }
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- { id: 2, class: sreg_64 }
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- { id: 3, class: sreg_128 }
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- { id: 4, class: sreg_32 }
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- { id: 5, class: sreg_32 }
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- { id: 6, class: sreg_64 }
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- { id: 7, class: sreg_128 }
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- { id: 8, class: sreg_64 }
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- { id: 9, class: sreg_128 }
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- { id: 10, class: sreg_128 }
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- { id: 11, class: sreg_64 }
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- { id: 12, class: sreg_128 }
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- { id: 13, class: sreg_64 }
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- { id: 14, class: sreg_64 }
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- { id: 15, class: sreg_128 }
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- { id: 16, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def %0
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S_NOP 0, implicit-def %1
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S_NOP 0, implicit-def %2
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%3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
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S_NOP 0, implicit %3.sub1
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S_NOP 0, implicit %3.sub3
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S_NOP 0, implicit-def %4
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S_NOP 0, implicit-def %5
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%6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1
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S_NOP 0, implicit %6
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S_NOP 0, implicit-def %7
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S_NOP 0, implicit-def %8
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%9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3
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S_NOP 0, implicit %9.sub2
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S_NOP 0, implicit-def %10
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S_NOP 0, implicit-def %11
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%12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1
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S_NOP 0, implicit %12.sub3
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S_NOP 0, implicit-def %13
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S_NOP 0, implicit-def %14
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%15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3
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%16 = EXTRACT_SUBREG %15, %subreg.sub0_sub1
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S_NOP 0, implicit %16.sub1
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...
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---
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# Check that copies to physregs use all lanes, copies from physregs define all
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# lanes. So we should not get a dead/undef flag here.
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# CHECK-LABEL: name: test3
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# CHECK: S_NOP 0, implicit-def %0
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# CHECK: %vcc = COPY %0
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# CHECK: %1 = COPY %vcc
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# CHECK: S_NOP 0, implicit %1
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name: test3
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_64 }
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- { id: 1, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def %0
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%vcc = COPY %0
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%1 = COPY %vcc
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S_NOP 0, implicit %1
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...
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---
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# Check that implicit-def/kill do not count as def/uses.
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# CHECK-LABEL: name: test4
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# CHECK: S_NOP 0, implicit-def dead %0
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# CHECK: KILL undef %0
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# CHECK: %1 = IMPLICIT_DEF
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# CHECK: S_NOP 0, implicit undef %1
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name: test4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_64 }
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- { id: 1, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def %0
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KILL %0
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%1 = IMPLICIT_DEF
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S_NOP 0, implicit %1
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...
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---
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# Check that unused inputs are marked as undef, even if the vreg itself is
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# used.
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# CHECK-LABEL: name: test5
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# CHECK: S_NOP 0, implicit-def %0
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# CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %1.sub1
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name: test5
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_32 }
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- { id: 1, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def %0
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%1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
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S_NOP 0, implicit %1.sub1
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...
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---
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# Check "optimistic" dataflow fixpoint in phi-loops.
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# CHECK-LABEL: name: loop0
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# CHECK: bb.0:
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# CHECK: S_NOP 0, implicit-def %0
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# CHECK: S_NOP 0, implicit-def dead %1
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# CHECK: S_NOP 0, implicit-def dead %2
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# CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
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# CHECK: bb.1:
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# CHECK: %4 = PHI %3, %bb.0, %5, %bb.1
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# CHECK: bb.2:
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# CHECK: S_NOP 0, implicit %4.sub0
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# CHECK: S_NOP 0, implicit undef %4.sub3
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name: loop0
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_32 }
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- { id: 1, class: sreg_32 }
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- { id: 2, class: sreg_32 }
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- { id: 3, class: sreg_128 }
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- { id: 4, class: sreg_128 }
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- { id: 5, class: sreg_128 }
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body: |
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bb.0:
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successors: %bb.1
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S_NOP 0, implicit-def %0
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S_NOP 0, implicit-def %1
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S_NOP 0, implicit-def %2
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%3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.1, %bb.2
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%4 = PHI %3, %bb.0, %5, %bb.1
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; let's swiffle some lanes around for fun...
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%5 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub2, %subreg.sub1, %4.sub1, %subreg.sub2, %4.sub3, %subreg.sub3
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.2:
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S_NOP 0, implicit %4.sub0
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S_NOP 0, implicit %4.sub3
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...
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---
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# Check a loop that needs to be traversed multiple times to reach the fixpoint
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# for the used lanes. The example reads sub3 lane at the end, however with each
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# loop iteration we should get 1 more lane marked as we cycles the sublanes
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# along. Sublanes sub0, sub1 and sub3 are rotate in the loop so only sub2
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# should be dead.
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# CHECK-LABEL: name: loop1
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# CHECK: bb.0:
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# CHECK: S_NOP 0, implicit-def %0
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# CHECK: S_NOP 0, implicit-def %1
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# CHECK: S_NOP 0, implicit-def dead %2
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# CHECK: S_NOP 0, implicit-def %3
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# CHECK: %4 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}}
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# CHECK: bb.1:
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# CHECK: %5 = PHI %4, %bb.0, %6, %bb.1
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# CHECK: %6 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
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# CHECK: bb.2:
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# CHECK: S_NOP 0, implicit %6.sub3
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name: loop1
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_32 }
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- { id: 1, class: sreg_32 }
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- { id: 2, class: sreg_32 }
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- { id: 3, class: sreg_32 }
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- { id: 4, class: sreg_128 }
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- { id: 5, class: sreg_128 }
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- { id: 6, class: sreg_128 }
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body: |
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bb.0:
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successors: %bb.1
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S_NOP 0, implicit-def %0
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S_NOP 0, implicit-def %1
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S_NOP 0, implicit-def dead %2
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S_NOP 0, implicit-def %3
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%4 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.1, %bb.2
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%5 = PHI %4, %bb.0, %6, %bb.1
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; rotate lanes, but skip sub2 lane...
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%6 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.2:
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S_NOP 0, implicit %6.sub3
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...
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---
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# Similar to loop1 test, but check for fixpoint of defined lanes.
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# Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef.
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# CHECK-LABEL: name: loop2
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# CHECK: bb.0:
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# CHECK: S_NOP 0, implicit-def %0
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# CHECK: %1 = REG_SEQUENCE %0, {{[0-9]+}}
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# CHECK: bb.1:
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# CHECK: %2 = PHI %1, %bb.0, %3, %bb.1
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# CHECK: %3 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
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# CHECK: bb.2:
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# CHECK: S_NOP 0, implicit %2.sub0
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# CHECK: S_NOP 0, implicit undef %2.sub1
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# CHECK: S_NOP 0, implicit %2.sub2
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# CHECK: S_NOP 0, implicit %2.sub3
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name: loop2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_32 }
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- { id: 1, class: sreg_128 }
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- { id: 2, class: sreg_128 }
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- { id: 3, class: sreg_128 }
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body: |
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bb.0:
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successors: %bb.1
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S_NOP 0, implicit-def %0
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%1 = REG_SEQUENCE %0, %subreg.sub0
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.1, %bb.2
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%2 = PHI %1, %bb.0, %3, %bb.1
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; rotate subreg lanes, skipping sub1
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%3 = REG_SEQUENCE %2.sub3, %subreg.sub0, %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.2:
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S_NOP 0, implicit %2.sub0
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S_NOP 0, implicit undef %2.sub1
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S_NOP 0, implicit %2.sub2
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S_NOP 0, implicit %2.sub3
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...
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