llvm-project/llvm/test/MC/Disassembler
Daniel Cederman 77611426e1 [Sparc] Add membar assembler tags
Summary: The Sparc V9 membar instruction can enforce different types of
memory orderings depending on the value in its immediate field.  In the
architectural manual the type is selected by combining different assembler
tags into a mask. This patch adds support for these tags.

Reviewers: jyknight, venkatra, brad

Reviewed By: jyknight

Subscribers: fedor.sergeev, jrtc27, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D53491

llvm-svn: 349048
2018-12-13 15:29:12 +00:00
..
AArch64 [AArch64] Add command-line option for SSBS 2018-12-03 14:00:47 +00:00
AMDGPU AMDGPU: Fix v_dot{4, 8}* instruction encoding 2018-05-15 19:32:47 +00:00
ARC [ARC] Prevent InstPrinter from crashing on unknown condition codes. 2018-09-06 19:58:26 +00:00
ARM [ARM][v8.5A] Add speculation barriers SSBB and PSSBB 2018-09-28 08:27:56 +00:00
Hexagon NFC - Various typo fixes in tests 2018-07-04 13:28:39 +00:00
Lanai
MSP430 [MSP430] Add MC layer 2018-11-15 12:29:43 +00:00
Mips [mips] Add missing instructions 2018-08-29 11:35:03 +00:00
PowerPC Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
RISCV [RISCV] Fix test/MC/Disassembler/RISCV/invalid-instruction.txt after rL347988 2018-12-03 10:35:46 +00:00
Sparc [Sparc] Add membar assembler tags 2018-12-13 15:29:12 +00:00
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
WebAssembly [WebAssembly] Read prefixed opcodes as ULEB128s 2018-11-09 01:57:00 +00:00
X86 [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16. 2018-10-02 18:16:19 +00:00
XCore