forked from OSchip/llvm-project
6067 lines
408 KiB
C++
6067 lines
408 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// Test host codegen.
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// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
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// RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
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// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
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// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
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// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6
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// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
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// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8
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#ifdef CK1
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template <typename T, int X, long long Y>
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struct SS{
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T a[X];
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float b;
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int foo(void) {
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#pragma omp target
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#pragma omp teams distribute
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for(int i = 0; i < X; i++) {
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a[i] = (T)0;
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}
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#pragma omp target
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#pragma omp teams distribute dist_schedule(static)
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for(int i = 0; i < X; i++) {
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a[i] = (T)0;
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}
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#pragma omp target
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#pragma omp teams distribute dist_schedule(static, X/2)
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for(int i = 0; i < X; i++) {
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a[i] = (T)0;
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}
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return a[0];
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}
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};
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int teams_template_struct(void) {
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SS<int, 123, 456> V;
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return V.foo();
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}
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#endif // CK1
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// Test host codegen.
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// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
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// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10
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// RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
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// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
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// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13
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// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14
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// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15
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// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16
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#ifdef CK2
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template <typename T, int n>
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int tmain(T argc) {
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T a[n];
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#pragma omp target
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#pragma omp teams distribute
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for(int i = 0; i < n; i++) {
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a[i] = (T)0;
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}
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#pragma omp target
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#pragma omp teams distribute dist_schedule(static)
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for(int i = 0; i < n; i++) {
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a[i] = (T)0;
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}
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#pragma omp target
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#pragma omp teams distribute dist_schedule(static, n)
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for(int i = 0; i < n; i++) {
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a[i] = (T)0;
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}
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return 0;
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}
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int main (int argc, char **argv) {
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int n = 100;
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int a[n];
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#pragma omp target
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#pragma omp teams distribute
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for(int i = 0; i < n; i++) {
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a[i] = 0;
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}
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#pragma omp target
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#pragma omp teams distribute dist_schedule(static)
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for(int i = 0; i < n; i++) {
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a[i] = 0;
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}
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#pragma omp target
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#pragma omp teams distribute dist_schedule(static, n)
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for(int i = 0; i < n; i++) {
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a[i] = 0;
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}
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return tmain<int, 10>(argc);
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}
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#endif // CK2
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#endif // #ifndef HEADER
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// CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
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// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]])
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// CHECK1-NEXT: ret i32 [[CALL]]
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
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// CHECK1-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[_TMP6:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [1 x i8*], align 8
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// CHECK1-NEXT: [[_TMP13:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
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// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
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// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
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// CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8
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// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]**
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// CHECK1-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8
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// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
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// CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8
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// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
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// CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123)
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// CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
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// CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
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// CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
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// CHECK1: omp_offload.failed:
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// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
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// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
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// CHECK1: omp_offload.cont:
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// CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS**
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// CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP10]], align 8
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// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [123 x i32]**
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// CHECK1-NEXT: store [123 x i32]* [[A2]], [123 x i32]** [[TMP12]], align 8
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// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0
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// CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
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// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
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// CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 123)
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// CHECK1-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
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// CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
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// CHECK1-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
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// CHECK1: omp_offload.failed7:
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// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33(%struct.SS* [[THIS1]]) #[[ATTR2]]
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// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]]
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// CHECK1: omp_offload.cont8:
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// CHECK1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.SS**
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// CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP19]], align 8
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// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [123 x i32]**
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// CHECK1-NEXT: store [123 x i32]* [[A9]], [123 x i32]** [[TMP21]], align 8
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// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
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// CHECK1-NEXT: store i8* null, i8** [[TMP22]], align 8
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// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
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// CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 123)
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// CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
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// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
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// CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
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// CHECK1: omp_offload.failed14:
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// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38(%struct.SS* [[THIS1]]) #[[ATTR2]]
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// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT15]]
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// CHECK1: omp_offload.cont15:
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// CHECK1-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
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// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 0
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// CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
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// CHECK1-NEXT: ret i32 [[TMP27]]
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
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// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
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// CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
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// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
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// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33
|
|
// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38
|
|
// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 61)
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK1: omp.dispatch.cond:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK1: omp.dispatch.body:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
|
|
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
|
|
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
|
|
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK1: omp.dispatch.inc:
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
|
|
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
|
|
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK1: omp.dispatch.end:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]])
|
|
// CHECK2-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK2-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[_TMP6:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK2-NEXT: [[_TMP13:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]**
|
|
// CHECK2-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP4]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123)
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS**
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP10]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [123 x i32]**
|
|
// CHECK2-NEXT: store [123 x i32]* [[A2]], [123 x i32]** [[TMP12]], align 8
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 123)
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK2: omp_offload.failed7:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33(%struct.SS* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK2: omp_offload.cont8:
|
|
// CHECK2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.SS**
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP19]], align 8
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [123 x i32]**
|
|
// CHECK2-NEXT: store [123 x i32]* [[A9]], [123 x i32]** [[TMP21]], align 8
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP22]], align 8
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 123)
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
|
|
// CHECK2: omp_offload.failed14:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38(%struct.SS* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT15]]
|
|
// CHECK2: omp_offload.cont15:
|
|
// CHECK2-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 0
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP27]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
|
|
// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33
|
|
// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38
|
|
// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 61)
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK2: omp.dispatch.cond:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK2: omp.dispatch.body:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
|
|
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
|
|
// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
|
|
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK2: omp.dispatch.inc:
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
|
|
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK2: omp.dispatch.end:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]])
|
|
// CHECK3-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK3-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[_TMP6:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK3-NEXT: [[_TMP13:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]**
|
|
// CHECK3-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123)
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS**
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [123 x i32]**
|
|
// CHECK3-NEXT: store [123 x i32]* [[A2]], [123 x i32]** [[TMP12]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 123)
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK3: omp_offload.failed7:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33(%struct.SS* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK3: omp_offload.cont8:
|
|
// CHECK3-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.SS**
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [123 x i32]**
|
|
// CHECK3-NEXT: store [123 x i32]* [[A9]], [123 x i32]** [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP22]], align 4
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 123)
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
|
|
// CHECK3: omp_offload.failed14:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38(%struct.SS* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT15]]
|
|
// CHECK3: omp_offload.cont15:
|
|
// CHECK3-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP27]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
|
|
// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP9]]
|
|
// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33
|
|
// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP9]]
|
|
// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38
|
|
// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 61)
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK3: omp.dispatch.cond:
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK3: omp.dispatch.body:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
|
|
// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]]
|
|
// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK3: omp.dispatch.inc:
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
|
|
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
|
|
// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK3: omp.dispatch.end:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]])
|
|
// CHECK4-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK4-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[_TMP6:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK4-NEXT: [[_TMP13:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS**
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x i32]**
|
|
// CHECK4-NEXT: store [123 x i32]* [[A]], [123 x i32]** [[TMP3]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP4]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 123)
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS**
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP10]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [123 x i32]**
|
|
// CHECK4-NEXT: store [123 x i32]* [[A2]], [123 x i32]** [[TMP12]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 123)
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK4: omp_offload.failed7:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33(%struct.SS* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK4: omp_offload.cont8:
|
|
// CHECK4-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.SS**
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP19]], align 4
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [123 x i32]**
|
|
// CHECK4-NEXT: store [123 x i32]* [[A9]], [123 x i32]** [[TMP21]], align 4
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP22]], align 4
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 123)
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
|
|
// CHECK4: omp_offload.failed14:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38(%struct.SS* [[THIS1]]) #[[ATTR2]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT15]]
|
|
// CHECK4: omp_offload.cont15:
|
|
// CHECK4-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP27]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
|
|
// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP9]]
|
|
// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33
|
|
// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP9]]
|
|
// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38
|
|
// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 122, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 61)
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK4: omp.dispatch.cond:
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK4: omp.dispatch.body:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
|
|
// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]]
|
|
// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
|
|
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK4: omp.dispatch.inc:
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
|
|
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
|
|
// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK4: omp.dispatch.end:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]])
|
|
// CHECK5-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK5-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[I2:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[I12:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK5-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK5: for.cond:
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123
|
|
// CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK5: for.body:
|
|
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
|
|
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK5: for.inc:
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
|
|
// CHECK5: for.end:
|
|
// CHECK5-NEXT: store i32 0, i32* [[I2]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_COND3:%.*]]
|
|
// CHECK5: for.cond3:
|
|
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK5-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123
|
|
// CHECK5-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]]
|
|
// CHECK5: for.body5:
|
|
// CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64
|
|
// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]]
|
|
// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_INC9:%.*]]
|
|
// CHECK5: for.inc9:
|
|
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK5-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK5-NEXT: store i32 [[INC10]], i32* [[I2]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK5: for.end11:
|
|
// CHECK5-NEXT: store i32 0, i32* [[I12]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_COND13:%.*]]
|
|
// CHECK5: for.cond13:
|
|
// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4
|
|
// CHECK5-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123
|
|
// CHECK5-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]]
|
|
// CHECK5: for.body15:
|
|
// CHECK5-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4
|
|
// CHECK5-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64
|
|
// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]]
|
|
// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_INC19:%.*]]
|
|
// CHECK5: for.inc19:
|
|
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4
|
|
// CHECK5-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK5-NEXT: store i32 [[INC20]], i32* [[I12]], align 4
|
|
// CHECK5-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]]
|
|
// CHECK5: for.end21:
|
|
// CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0
|
|
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4
|
|
// CHECK5-NEXT: ret i32 [[TMP9]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]])
|
|
// CHECK6-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK6-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8
|
|
// CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[I2:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[I12:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8
|
|
// CHECK6-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK6: for.cond:
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123
|
|
// CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK6: for.body:
|
|
// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
|
|
// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK6: for.inc:
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
|
|
// CHECK6: for.end:
|
|
// CHECK6-NEXT: store i32 0, i32* [[I2]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_COND3:%.*]]
|
|
// CHECK6: for.cond3:
|
|
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK6-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123
|
|
// CHECK6-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END11:%.*]]
|
|
// CHECK6: for.body5:
|
|
// CHECK6-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP4]] to i64
|
|
// CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i64 0, i64 [[IDXPROM7]]
|
|
// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_INC9:%.*]]
|
|
// CHECK6: for.inc9:
|
|
// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK6-NEXT: [[INC10:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK6-NEXT: store i32 [[INC10]], i32* [[I2]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK6: for.end11:
|
|
// CHECK6-NEXT: store i32 0, i32* [[I12]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_COND13:%.*]]
|
|
// CHECK6: for.cond13:
|
|
// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I12]], align 4
|
|
// CHECK6-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP6]], 123
|
|
// CHECK6-NEXT: br i1 [[CMP14]], label [[FOR_BODY15:%.*]], label [[FOR_END21:%.*]]
|
|
// CHECK6: for.body15:
|
|
// CHECK6-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I12]], align 4
|
|
// CHECK6-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP7]] to i64
|
|
// CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A16]], i64 0, i64 [[IDXPROM17]]
|
|
// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX18]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_INC19:%.*]]
|
|
// CHECK6: for.inc19:
|
|
// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I12]], align 4
|
|
// CHECK6-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK6-NEXT: store i32 [[INC20]], i32* [[I12]], align 4
|
|
// CHECK6-NEXT: br label [[FOR_COND13]], !llvm.loop [[LOOP5:![0-9]+]]
|
|
// CHECK6: for.end21:
|
|
// CHECK6-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A22]], i64 0, i64 0
|
|
// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX23]], align 4
|
|
// CHECK6-NEXT: ret i32 [[TMP9]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]])
|
|
// CHECK7-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK7-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[I2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[I11:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK7: for.cond:
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123
|
|
// CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK7: for.body:
|
|
// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]]
|
|
// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK7: for.inc:
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK7: for.end:
|
|
// CHECK7-NEXT: store i32 0, i32* [[I2]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_COND3:%.*]]
|
|
// CHECK7: for.cond3:
|
|
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK7-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123
|
|
// CHECK7-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]]
|
|
// CHECK7: for.body5:
|
|
// CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]]
|
|
// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_INC8:%.*]]
|
|
// CHECK7: for.inc8:
|
|
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK7-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK7-NEXT: store i32 [[INC9]], i32* [[I2]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
|
|
// CHECK7: for.end10:
|
|
// CHECK7-NEXT: store i32 0, i32* [[I11]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_COND12:%.*]]
|
|
// CHECK7: for.cond12:
|
|
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4
|
|
// CHECK7-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123
|
|
// CHECK7-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]]
|
|
// CHECK7: for.body14:
|
|
// CHECK7-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4
|
|
// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]]
|
|
// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_INC17:%.*]]
|
|
// CHECK7: for.inc17:
|
|
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4
|
|
// CHECK7-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK7-NEXT: store i32 [[INC18]], i32* [[I11]], align 4
|
|
// CHECK7-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]]
|
|
// CHECK7: for.end19:
|
|
// CHECK7-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0
|
|
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4
|
|
// CHECK7-NEXT: ret i32 [[TMP9]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv
|
|
// CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
|
|
// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(496) [[V]])
|
|
// CHECK8-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
|
|
// CHECK8-SAME: (%struct.SS* nonnull dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK8-NEXT: entry:
|
|
// CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4
|
|
// CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[I2:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: [[I11:%.*]] = alloca i32, align 4
|
|
// CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4
|
|
// CHECK8-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK8: for.cond:
|
|
// CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 123
|
|
// CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK8: for.body:
|
|
// CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP1]]
|
|
// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK8: for.inc:
|
|
// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK8: for.end:
|
|
// CHECK8-NEXT: store i32 0, i32* [[I2]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_COND3:%.*]]
|
|
// CHECK8: for.cond3:
|
|
// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK8-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP3]], 123
|
|
// CHECK8-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END10:%.*]]
|
|
// CHECK8: for.body5:
|
|
// CHECK8-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A6]], i32 0, i32 [[TMP4]]
|
|
// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_INC8:%.*]]
|
|
// CHECK8: for.inc8:
|
|
// CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I2]], align 4
|
|
// CHECK8-NEXT: [[INC9:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK8-NEXT: store i32 [[INC9]], i32* [[I2]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP5:![0-9]+]]
|
|
// CHECK8: for.end10:
|
|
// CHECK8-NEXT: store i32 0, i32* [[I11]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_COND12:%.*]]
|
|
// CHECK8: for.cond12:
|
|
// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I11]], align 4
|
|
// CHECK8-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP6]], 123
|
|
// CHECK8-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END19:%.*]]
|
|
// CHECK8: for.body14:
|
|
// CHECK8-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I11]], align 4
|
|
// CHECK8-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A15]], i32 0, i32 [[TMP7]]
|
|
// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX16]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_INC17:%.*]]
|
|
// CHECK8: for.inc17:
|
|
// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I11]], align 4
|
|
// CHECK8-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK8-NEXT: store i32 [[INC18]], i32* [[I11]], align 4
|
|
// CHECK8-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP6:![0-9]+]]
|
|
// CHECK8: for.end19:
|
|
// CHECK8-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A20]], i32 0, i32 0
|
|
// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX21]], align 4
|
|
// CHECK8-NEXT: ret i32 [[TMP9]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@main
|
|
// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
|
|
// CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8
|
|
// CHECK9-NEXT: [[_TMP9:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_SIZES23:%.*]] = alloca [3 x i64], align 8
|
|
// CHECK9-NEXT: [[_TMP24:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 100, i32* [[N]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK9-NEXT: store i64 4, i64* [[TMP10]], align 8
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK9-NEXT: store i64 8, i64* [[TMP16]], align 8
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
|
|
// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
|
|
// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8
|
|
// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK9-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8
|
|
// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0
|
|
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1
|
|
// CHECK9-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64
|
|
// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]])
|
|
// CHECK9-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK9: omp_offload.failed:
|
|
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
|
|
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK9: omp_offload.cont:
|
|
// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4
|
|
// CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8
|
|
// CHECK9-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4
|
|
// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8
|
|
// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8
|
|
// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0
|
|
// CHECK9-NEXT: store i64 4, i64* [[TMP40]], align 8
|
|
// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP41]], align 8
|
|
// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8
|
|
// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8
|
|
// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1
|
|
// CHECK9-NEXT: store i64 8, i64* [[TMP46]], align 8
|
|
// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP47]], align 8
|
|
// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32**
|
|
// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8
|
|
// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32**
|
|
// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8
|
|
// CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2
|
|
// CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8
|
|
// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP53]], align 8
|
|
// CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4
|
|
// CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4
|
|
// CHECK9-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0
|
|
// CHECK9-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
|
|
// CHECK9-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1
|
|
// CHECK9-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4
|
|
// CHECK9-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4
|
|
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK9-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64
|
|
// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]])
|
|
// CHECK9-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK9-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
|
|
// CHECK9: omp_offload.failed16:
|
|
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]]
|
|
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT17]]
|
|
// CHECK9: omp_offload.cont17:
|
|
// CHECK9-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK9-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP63]], i32* [[CONV19]], align 4
|
|
// CHECK9-NEXT: [[TMP64:%.*]] = load i64, i64* [[N_CASTED18]], align 8
|
|
// CHECK9-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP1]], 4
|
|
// CHECK9-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP67]], align 8
|
|
// CHECK9-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8
|
|
// CHECK9-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0
|
|
// CHECK9-NEXT: store i64 4, i64* [[TMP70]], align 8
|
|
// CHECK9-NEXT: [[TMP71:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP71]], align 8
|
|
// CHECK9-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP73]], align 8
|
|
// CHECK9-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64*
|
|
// CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP75]], align 8
|
|
// CHECK9-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 1
|
|
// CHECK9-NEXT: store i64 8, i64* [[TMP76]], align 8
|
|
// CHECK9-NEXT: [[TMP77:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP77]], align 8
|
|
// CHECK9-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32**
|
|
// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP79]], align 8
|
|
// CHECK9-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK9-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32**
|
|
// CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 8
|
|
// CHECK9-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 2
|
|
// CHECK9-NEXT: store i64 [[TMP65]], i64* [[TMP82]], align 8
|
|
// CHECK9-NEXT: [[TMP83:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP83]], align 8
|
|
// CHECK9-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP87:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_25]], align 4
|
|
// CHECK9-NEXT: [[TMP88:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4
|
|
// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP88]], 0
|
|
// CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
|
|
// CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[DIV28]], 1
|
|
// CHECK9-NEXT: store i32 [[SUB29]], i32* [[DOTCAPTURE_EXPR_26]], align 4
|
|
// CHECK9-NEXT: [[TMP89:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4
|
|
// CHECK9-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP89]], 1
|
|
// CHECK9-NEXT: [[TMP90:%.*]] = zext i32 [[ADD30]] to i64
|
|
// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP90]])
|
|
// CHECK9-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP84]], i8** [[TMP85]], i64* [[TMP86]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK9-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
|
|
// CHECK9: omp_offload.failed31:
|
|
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP64]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]]
|
|
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]]
|
|
// CHECK9: omp_offload.cont32:
|
|
// CHECK9-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
|
|
// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]])
|
|
// CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
|
|
// CHECK9-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP94]])
|
|
// CHECK9-NEXT: [[TMP95:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
// CHECK9-NEXT: ret i32 [[TMP95]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
|
|
// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK9: omp.precond.then:
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
|
|
// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4
|
|
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]]
|
|
// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
|
|
// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK9: omp.precond.end:
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105
|
|
// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I3:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK9-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK9: omp.precond.then:
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
|
|
// CHECK9-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4
|
|
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]]
|
|
// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
|
|
// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK9: omp.precond.end:
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110
|
|
// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK9: omp.precond.then:
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK9: omp.dispatch.cond:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
|
|
// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
|
|
// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK9: omp.dispatch.body:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
|
|
// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
|
|
// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !10
|
|
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]]
|
|
// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK9: omp.dispatch.inc:
|
|
// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
|
|
// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
|
|
// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK9: omp.dispatch.end:
|
|
// CHECK9-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]])
|
|
// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK9: omp.precond.end:
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
|
|
// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK9-NEXT: [[_TMP10:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]**
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]**
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK9: omp_offload.failed:
|
|
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK9: omp_offload.cont:
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]**
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
|
// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
|
|
// CHECK9: omp_offload.failed5:
|
|
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]]
|
|
// CHECK9: omp_offload.cont6:
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]**
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]**
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8
|
|
// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
|
|
// CHECK9-NEXT: store i8* null, i8** [[TMP22]], align 8
|
|
// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK9-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK9-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
|
|
// CHECK9: omp_offload.failed11:
|
|
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT12]]
|
|
// CHECK9: omp_offload.cont12:
|
|
// CHECK9-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79
|
|
// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84
|
|
// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89
|
|
// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10)
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK9: omp.dispatch.cond:
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK9: omp.dispatch.body:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
|
|
// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13
|
|
// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK9: omp.dispatch.inc:
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
|
|
// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
|
|
// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK9: omp.dispatch.end:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK9-SAME: () #[[ATTR5:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@main
|
|
// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
|
|
// CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_SIZES8:%.*]] = alloca [3 x i64], align 8
|
|
// CHECK10-NEXT: [[_TMP9:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[N_CASTED18:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_SIZES23:%.*]] = alloca [3 x i64], align 8
|
|
// CHECK10-NEXT: [[_TMP24:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32 100, i32* [[N]], align 4
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK10-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP7]], align 8
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP9]], align 8
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK10-NEXT: store i64 4, i64* [[TMP10]], align 8
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK10-NEXT: store i64 8, i64* [[TMP16]], align 8
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
|
|
// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 8
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
|
|
// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 8
|
|
// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK10-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8
|
|
// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0
|
|
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1
|
|
// CHECK10-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64
|
|
// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]])
|
|
// CHECK10-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK10: omp_offload.failed:
|
|
// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i64 [[TMP4]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
|
|
// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK10: omp_offload.cont:
|
|
// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED3]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4
|
|
// CHECK10-NEXT: [[TMP34:%.*]] = load i64, i64* [[N_CASTED3]], align 8
|
|
// CHECK10-NEXT: [[TMP35:%.*]] = mul nuw i64 [[TMP1]], 4
|
|
// CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP37]], align 8
|
|
// CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8
|
|
// CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0
|
|
// CHECK10-NEXT: store i64 4, i64* [[TMP40]], align 8
|
|
// CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP41]], align 8
|
|
// CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP43]], align 8
|
|
// CHECK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP45]], align 8
|
|
// CHECK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 1
|
|
// CHECK10-NEXT: store i64 8, i64* [[TMP46]], align 8
|
|
// CHECK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP47]], align 8
|
|
// CHECK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32**
|
|
// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP49]], align 8
|
|
// CHECK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32**
|
|
// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP51]], align 8
|
|
// CHECK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 2
|
|
// CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP52]], align 8
|
|
// CHECK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 2
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP53]], align 8
|
|
// CHECK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES8]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP57:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP57]], i32* [[DOTCAPTURE_EXPR_10]], align 4
|
|
// CHECK10-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4
|
|
// CHECK10-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP58]], 0
|
|
// CHECK10-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
|
|
// CHECK10-NEXT: [[SUB14:%.*]] = sub nsw i32 [[DIV13]], 1
|
|
// CHECK10-NEXT: store i32 [[SUB14]], i32* [[DOTCAPTURE_EXPR_11]], align 4
|
|
// CHECK10-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_11]], align 4
|
|
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP59]], 1
|
|
// CHECK10-NEXT: [[TMP60:%.*]] = zext i32 [[ADD15]] to i64
|
|
// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP60]])
|
|
// CHECK10-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP54]], i8** [[TMP55]], i64* [[TMP56]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK10-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
|
|
// CHECK10: omp_offload.failed16:
|
|
// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP34]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]]
|
|
// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT17]]
|
|
// CHECK10: omp_offload.cont17:
|
|
// CHECK10-NEXT: [[TMP63:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK10-NEXT: [[CONV19:%.*]] = bitcast i64* [[N_CASTED18]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP63]], i32* [[CONV19]], align 4
|
|
// CHECK10-NEXT: [[TMP64:%.*]] = load i64, i64* [[N_CASTED18]], align 8
|
|
// CHECK10-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP1]], 4
|
|
// CHECK10-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP67]], align 8
|
|
// CHECK10-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP64]], i64* [[TMP69]], align 8
|
|
// CHECK10-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0
|
|
// CHECK10-NEXT: store i64 4, i64* [[TMP70]], align 8
|
|
// CHECK10-NEXT: [[TMP71:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP71]], align 8
|
|
// CHECK10-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP73]], align 8
|
|
// CHECK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i64*
|
|
// CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP75]], align 8
|
|
// CHECK10-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 1
|
|
// CHECK10-NEXT: store i64 8, i64* [[TMP76]], align 8
|
|
// CHECK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP77]], align 8
|
|
// CHECK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32**
|
|
// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP79]], align 8
|
|
// CHECK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK10-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32**
|
|
// CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 8
|
|
// CHECK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 2
|
|
// CHECK10-NEXT: store i64 [[TMP65]], i64* [[TMP82]], align 8
|
|
// CHECK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP83]], align 8
|
|
// CHECK10-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES23]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP87:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_25]], align 4
|
|
// CHECK10-NEXT: [[TMP88:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_25]], align 4
|
|
// CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP88]], 0
|
|
// CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
|
|
// CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[DIV28]], 1
|
|
// CHECK10-NEXT: store i32 [[SUB29]], i32* [[DOTCAPTURE_EXPR_26]], align 4
|
|
// CHECK10-NEXT: [[TMP89:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_26]], align 4
|
|
// CHECK10-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP89]], 1
|
|
// CHECK10-NEXT: [[TMP90:%.*]] = zext i32 [[ADD30]] to i64
|
|
// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP90]])
|
|
// CHECK10-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP84]], i8** [[TMP85]], i64* [[TMP86]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK10-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
|
|
// CHECK10: omp_offload.failed31:
|
|
// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP64]], i64 [[TMP1]], i32* [[VLA]]) #[[ATTR3]]
|
|
// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT32]]
|
|
// CHECK10: omp_offload.cont32:
|
|
// CHECK10-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
|
|
// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]])
|
|
// CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
|
|
// CHECK10-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP94]])
|
|
// CHECK10-NEXT: [[TMP95:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
// CHECK10-NEXT: ret i32 [[TMP95]]
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
|
|
// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK10: omp.precond.then:
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
|
|
// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4
|
|
// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]]
|
|
// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
|
|
// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK10: omp.precond.end:
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105
|
|
// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK10: omp.precond.then:
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
|
|
// CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4
|
|
// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]]
|
|
// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
|
|
// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK10: omp.precond.end:
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110
|
|
// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[CONV]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP4]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I4:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK10: omp.precond.then:
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK10: omp.dispatch.cond:
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
|
|
// CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
|
|
// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK10: omp.dispatch.body:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
|
|
// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
|
|
// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !10
|
|
// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]]
|
|
// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK10: omp.dispatch.inc:
|
|
// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
|
|
// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
|
|
// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK10: omp.dispatch.end:
|
|
// CHECK10-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]])
|
|
// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK10: omp.precond.end:
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
|
|
// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 8
|
|
// CHECK10-NEXT: [[_TMP10:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]**
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]**
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 8
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK10: omp_offload.failed:
|
|
// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK10: omp_offload.cont:
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 8
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]**
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 8
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
|
// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
|
|
// CHECK10: omp_offload.failed5:
|
|
// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]]
|
|
// CHECK10: omp_offload.cont6:
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]**
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 8
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]**
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 8
|
|
// CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
|
|
// CHECK10-NEXT: store i8* null, i8** [[TMP22]], align 8
|
|
// CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK10-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK10-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
|
|
// CHECK10: omp_offload.failed11:
|
|
// CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT12]]
|
|
// CHECK10: omp_offload.cont12:
|
|
// CHECK10-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79
|
|
// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84
|
|
// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89
|
|
// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10)
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK10: omp.dispatch.cond:
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK10: omp.dispatch.body:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
|
|
// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !13
|
|
// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK10: omp.dispatch.inc:
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
|
|
// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
|
|
// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK10: omp.dispatch.end:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK10-SAME: () #[[ATTR5:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@main
|
|
// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
|
|
// CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4
|
|
// CHECK11-NEXT: [[_TMP8:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [3 x i64], align 4
|
|
// CHECK11-NEXT: [[_TMP22:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 100, i32* [[N]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i64 4, i64* [[TMP10]], align 4
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK11-NEXT: store i64 4, i64* [[TMP16]], align 4
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP17]], align 4
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
|
|
// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
|
|
// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4
|
|
// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK11-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4
|
|
// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4
|
|
// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0
|
|
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1
|
|
// CHECK11-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64
|
|
// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]])
|
|
// CHECK11-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK11: omp_offload.failed:
|
|
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
|
|
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK11: omp_offload.cont:
|
|
// CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4
|
|
// CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4
|
|
// CHECK11-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4
|
|
// CHECK11-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4
|
|
// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4
|
|
// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i64 4, i64* [[TMP41]], align 4
|
|
// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP42]], align 4
|
|
// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4
|
|
// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4
|
|
// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1
|
|
// CHECK11-NEXT: store i64 4, i64* [[TMP47]], align 4
|
|
// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP48]], align 4
|
|
// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32**
|
|
// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4
|
|
// CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32**
|
|
// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4
|
|
// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2
|
|
// CHECK11-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4
|
|
// CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP54]], align 4
|
|
// CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4
|
|
// CHECK11-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4
|
|
// CHECK11-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0
|
|
// CHECK11-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1
|
|
// CHECK11-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1
|
|
// CHECK11-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4
|
|
// CHECK11-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4
|
|
// CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1
|
|
// CHECK11-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64
|
|
// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]])
|
|
// CHECK11-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK11-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
|
|
// CHECK11: omp_offload.failed15:
|
|
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]]
|
|
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT16]]
|
|
// CHECK11: omp_offload.cont16:
|
|
// CHECK11-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP64]], i32* [[N_CASTED17]], align 4
|
|
// CHECK11-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_CASTED17]], align 4
|
|
// CHECK11-NEXT: [[TMP66:%.*]] = mul nuw i32 [[TMP0]], 4
|
|
// CHECK11-NEXT: [[TMP67:%.*]] = sext i32 [[TMP66]] to i64
|
|
// CHECK11-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP65]], i32* [[TMP69]], align 4
|
|
// CHECK11-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4
|
|
// CHECK11-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i64 4, i64* [[TMP72]], align 4
|
|
// CHECK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP73]], align 4
|
|
// CHECK11-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP75]], align 4
|
|
// CHECK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32*
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP77]], align 4
|
|
// CHECK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1
|
|
// CHECK11-NEXT: store i64 4, i64* [[TMP78]], align 4
|
|
// CHECK11-NEXT: [[TMP79:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP79]], align 4
|
|
// CHECK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32**
|
|
// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 4
|
|
// CHECK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32**
|
|
// CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP83]], align 4
|
|
// CHECK11-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2
|
|
// CHECK11-NEXT: store i64 [[TMP67]], i64* [[TMP84]], align 4
|
|
// CHECK11-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP85]], align 4
|
|
// CHECK11-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP87:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP88:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP89:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_23]], align 4
|
|
// CHECK11-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4
|
|
// CHECK11-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP90]], 0
|
|
// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1
|
|
// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1
|
|
// CHECK11-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4
|
|
// CHECK11-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4
|
|
// CHECK11-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP91]], 1
|
|
// CHECK11-NEXT: [[TMP92:%.*]] = zext i32 [[ADD28]] to i64
|
|
// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP92]])
|
|
// CHECK11-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP86]], i8** [[TMP87]], i64* [[TMP88]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK11-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]]
|
|
// CHECK11: omp_offload.failed29:
|
|
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP65]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]]
|
|
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT30]]
|
|
// CHECK11: omp_offload.cont30:
|
|
// CHECK11-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]])
|
|
// CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
|
|
// CHECK11-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP96]])
|
|
// CHECK11-NEXT: [[TMP97:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
// CHECK11-NEXT: ret i32 [[TMP97]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
|
|
// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK11: omp.precond.then:
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
|
|
// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]]
|
|
// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
|
|
// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK11: omp.precond.end:
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105
|
|
// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK11: omp.precond.then:
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
|
|
// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]]
|
|
// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
|
|
// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK11: omp.precond.end:
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110
|
|
// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I4:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK11: omp.precond.then:
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK11: omp.dispatch.cond:
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
|
|
// CHECK11-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
|
|
// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK11: omp.dispatch.body:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
|
|
// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]]
|
|
// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK11: omp.dispatch.inc:
|
|
// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
|
|
// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
|
|
// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK11: omp.dispatch.end:
|
|
// CHECK11-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]])
|
|
// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK11: omp.precond.end:
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
|
|
// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK11-NEXT: [[_TMP10:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]**
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]**
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK11: omp_offload.failed:
|
|
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK11: omp_offload.cont:
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]**
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
|
// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
|
|
// CHECK11: omp_offload.failed5:
|
|
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]]
|
|
// CHECK11: omp_offload.cont6:
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]**
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]**
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4
|
|
// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0
|
|
// CHECK11-NEXT: store i8* null, i8** [[TMP22]], align 4
|
|
// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK11-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK11-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
|
|
// CHECK11: omp_offload.failed11:
|
|
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT12]]
|
|
// CHECK11: omp_offload.cont12:
|
|
// CHECK11-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79
|
|
// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]]
|
|
// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84
|
|
// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]]
|
|
// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89
|
|
// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10)
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK11: omp.dispatch.cond:
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK11: omp.dispatch.body:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
|
|
// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]]
|
|
// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
|
|
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK11: omp.dispatch.inc:
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
|
|
// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
|
|
// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK11: omp.dispatch.end:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK11-SAME: () #[[ATTR5:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@main
|
|
// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
|
|
// CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[N_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_SIZES7:%.*]] = alloca [3 x i64], align 4
|
|
// CHECK12-NEXT: [[_TMP8:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_10:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[N_CASTED17:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_PTRS19:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_SIZES21:%.*]] = alloca [3 x i64], align 4
|
|
// CHECK12-NEXT: [[_TMP22:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_23:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 100, i32* [[N]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP7]], align 4
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP9]], align 4
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i64 4, i64* [[TMP10]], align 4
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP13]], align 4
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP15]], align 4
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
|
|
// CHECK12-NEXT: store i64 4, i64* [[TMP16]], align 4
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP17]], align 4
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
|
|
// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP19]], align 4
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
|
|
// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP21]], align 4
|
|
// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
|
|
// CHECK12-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 4
|
|
// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4
|
|
// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP27]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP28]], 0
|
|
// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], 1
|
|
// CHECK12-NEXT: [[TMP30:%.*]] = zext i32 [[ADD]] to i64
|
|
// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[TMP30]])
|
|
// CHECK12-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* [[TMP26]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK12: omp_offload.failed:
|
|
// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100(i32 [[TMP3]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3:[0-9]+]]
|
|
// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK12: omp_offload.cont:
|
|
// CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP33]], i32* [[N_CASTED3]], align 4
|
|
// CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[N_CASTED3]], align 4
|
|
// CHECK12-NEXT: [[TMP35:%.*]] = mul nuw i32 [[TMP0]], 4
|
|
// CHECK12-NEXT: [[TMP36:%.*]] = sext i32 [[TMP35]] to i64
|
|
// CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP38]], align 4
|
|
// CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP40]], align 4
|
|
// CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i64 4, i64* [[TMP41]], align 4
|
|
// CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP42]], align 4
|
|
// CHECK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP44]], align 4
|
|
// CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP46]], align 4
|
|
// CHECK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 1
|
|
// CHECK12-NEXT: store i64 4, i64* [[TMP47]], align 4
|
|
// CHECK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP48]], align 4
|
|
// CHECK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32**
|
|
// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP50]], align 4
|
|
// CHECK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32**
|
|
// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP52]], align 4
|
|
// CHECK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 2
|
|
// CHECK12-NEXT: store i64 [[TMP36]], i64* [[TMP53]], align 4
|
|
// CHECK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 2
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP54]], align 4
|
|
// CHECK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES7]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP58:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR_9]], align 4
|
|
// CHECK12-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_9]], align 4
|
|
// CHECK12-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP59]], 0
|
|
// CHECK12-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1
|
|
// CHECK12-NEXT: [[SUB13:%.*]] = sub nsw i32 [[DIV12]], 1
|
|
// CHECK12-NEXT: store i32 [[SUB13]], i32* [[DOTCAPTURE_EXPR_10]], align 4
|
|
// CHECK12-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_10]], align 4
|
|
// CHECK12-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP60]], 1
|
|
// CHECK12-NEXT: [[TMP61:%.*]] = zext i32 [[ADD14]] to i64
|
|
// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP61]])
|
|
// CHECK12-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105.region_id, i32 3, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK12-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
|
|
// CHECK12: omp_offload.failed15:
|
|
// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP34]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]]
|
|
// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT16]]
|
|
// CHECK12: omp_offload.cont16:
|
|
// CHECK12-NEXT: [[TMP64:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP64]], i32* [[N_CASTED17]], align 4
|
|
// CHECK12-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_CASTED17]], align 4
|
|
// CHECK12-NEXT: [[TMP66:%.*]] = mul nuw i32 [[TMP0]], 4
|
|
// CHECK12-NEXT: [[TMP67:%.*]] = sext i32 [[TMP66]] to i64
|
|
// CHECK12-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP65]], i32* [[TMP69]], align 4
|
|
// CHECK12-NEXT: [[TMP70:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP65]], i32* [[TMP71]], align 4
|
|
// CHECK12-NEXT: [[TMP72:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i64 4, i64* [[TMP72]], align 4
|
|
// CHECK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP73]], align 4
|
|
// CHECK12-NEXT: [[TMP74:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP75]], align 4
|
|
// CHECK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32*
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP77]], align 4
|
|
// CHECK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 1
|
|
// CHECK12-NEXT: store i64 4, i64* [[TMP78]], align 4
|
|
// CHECK12-NEXT: [[TMP79:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP79]], align 4
|
|
// CHECK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32**
|
|
// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP81]], align 4
|
|
// CHECK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32**
|
|
// CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP83]], align 4
|
|
// CHECK12-NEXT: [[TMP84:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 2
|
|
// CHECK12-NEXT: store i64 [[TMP67]], i64* [[TMP84]], align 4
|
|
// CHECK12-NEXT: [[TMP85:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 2
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP85]], align 4
|
|
// CHECK12-NEXT: [[TMP86:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP87:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS19]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP88:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[DOTOFFLOAD_SIZES21]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP89:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_23]], align 4
|
|
// CHECK12-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_23]], align 4
|
|
// CHECK12-NEXT: [[SUB25:%.*]] = sub nsw i32 [[TMP90]], 0
|
|
// CHECK12-NEXT: [[DIV26:%.*]] = sdiv i32 [[SUB25]], 1
|
|
// CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[DIV26]], 1
|
|
// CHECK12-NEXT: store i32 [[SUB27]], i32* [[DOTCAPTURE_EXPR_24]], align 4
|
|
// CHECK12-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_24]], align 4
|
|
// CHECK12-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP91]], 1
|
|
// CHECK12-NEXT: [[TMP92:%.*]] = zext i32 [[ADD28]] to i64
|
|
// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP92]])
|
|
// CHECK12-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110.region_id, i32 3, i8** [[TMP86]], i8** [[TMP87]], i64* [[TMP88]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK12-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED29:%.*]], label [[OMP_OFFLOAD_CONT30:%.*]]
|
|
// CHECK12: omp_offload.failed29:
|
|
// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP65]], i32 [[TMP0]], i32* [[VLA]]) #[[ATTR3]]
|
|
// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT30]]
|
|
// CHECK12: omp_offload.cont30:
|
|
// CHECK12-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]])
|
|
// CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
|
|
// CHECK12-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP96]])
|
|
// CHECK12-NEXT: [[TMP97:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
// CHECK12-NEXT: ret i32 [[TMP97]]
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
|
|
// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK12: omp.precond.then:
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
|
|
// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]]
|
|
// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
|
|
// CHECK12-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK12: omp.precond.end:
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105
|
|
// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK12: omp.precond.then:
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
|
|
// CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP17]]
|
|
// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
|
|
// CHECK12-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK12: omp.precond.end:
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110
|
|
// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP4]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I4:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
|
|
// CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
|
|
// CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
|
|
// CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
|
|
// CHECK12: omp.precond.then:
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK12: omp.dispatch.cond:
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
|
|
// CHECK12-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
|
|
// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK12: omp.dispatch.body:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
|
|
// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
|
|
// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !11
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP20]]
|
|
// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK12: omp.dispatch.inc:
|
|
// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
|
|
// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
|
|
// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK12: omp.dispatch.end:
|
|
// CHECK12-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]])
|
|
// CHECK12-NEXT: br label [[OMP_PRECOND_END]]
|
|
// CHECK12: omp.precond.end:
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
|
|
// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[_TMP4:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x i8*], align 4
|
|
// CHECK12-NEXT: [[_TMP10:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x i32]**
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP1]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x i32]**
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP3]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK12: omp_offload.failed:
|
|
// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK12: omp_offload.cont:
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP10]], align 4
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [10 x i32]**
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP12]], align 4
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
|
|
// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84.region_id, i32 1, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
|
|
// CHECK12: omp_offload.failed5:
|
|
// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]]
|
|
// CHECK12: omp_offload.cont6:
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to [10 x i32]**
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP19]], align 4
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to [10 x i32]**
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[TMP21]], align 4
|
|
// CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0
|
|
// CHECK12-NEXT: store i8* null, i8** [[TMP22]], align 4
|
|
// CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
|
|
// CHECK12-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89.region_id, i32 1, i8** [[TMP23]], i8** [[TMP24]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
|
|
// CHECK12-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
|
|
// CHECK12: omp_offload.failed11:
|
|
// CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89([10 x i32]* [[A]]) #[[ATTR3]]
|
|
// CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT12]]
|
|
// CHECK12: omp_offload.cont12:
|
|
// CHECK12-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79
|
|
// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]]
|
|
// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84
|
|
// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP9]]
|
|
// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89
|
|
// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), [10 x i32]* [[TMP0]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 10)
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK12: omp.dispatch.cond:
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK12: omp.dispatch.body:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
|
|
// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
|
|
// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !14
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]]
|
|
// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
|
|
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK12: omp.dispatch.inc:
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
|
|
// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
|
|
// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK12: omp.dispatch.end:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@main
|
|
// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
|
|
// CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
|
|
// CHECK13-NEXT: store i32 100, i32* [[N]], align 4
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
|
|
// CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK13: for.cond:
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]]
|
|
// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK13: for.body:
|
|
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
|
|
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]]
|
|
// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK13: for.inc:
|
|
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
|
|
// CHECK13: for.end:
|
|
// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND2:%.*]]
|
|
// CHECK13: for.cond2:
|
|
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]
|
|
// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]]
|
|
// CHECK13: for.body4:
|
|
// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]]
|
|
// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_INC7:%.*]]
|
|
// CHECK13: for.inc7:
|
|
// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK13: for.end9:
|
|
// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND11:%.*]]
|
|
// CHECK13: for.cond11:
|
|
// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]]
|
|
// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
|
|
// CHECK13: for.body13:
|
|
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64
|
|
// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]]
|
|
// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_INC16:%.*]]
|
|
// CHECK13: for.inc16:
|
|
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
|
|
// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
|
|
// CHECK13: for.end18:
|
|
// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
|
|
// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]])
|
|
// CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
|
|
// CHECK13-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP17]])
|
|
// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
// CHECK13-NEXT: ret i32 [[TMP18]]
|
|
//
|
|
//
|
|
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
|
|
// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
|
|
// CHECK13-NEXT: entry:
|
|
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[I1:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: [[I10:%.*]] = alloca i32, align 4
|
|
// CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK13-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK13: for.cond:
|
|
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
|
|
// CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK13: for.body:
|
|
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
|
|
// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK13: for.inc:
|
|
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
|
|
// CHECK13: for.end:
|
|
// CHECK13-NEXT: store i32 0, i32* [[I1]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND2:%.*]]
|
|
// CHECK13: for.cond2:
|
|
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK13-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10
|
|
// CHECK13-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]]
|
|
// CHECK13: for.body4:
|
|
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64
|
|
// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]]
|
|
// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_INC7:%.*]]
|
|
// CHECK13: for.inc7:
|
|
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK13-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK13-NEXT: store i32 [[INC8]], i32* [[I1]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK13: for.end9:
|
|
// CHECK13-NEXT: store i32 0, i32* [[I10]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND11:%.*]]
|
|
// CHECK13: for.cond11:
|
|
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK13-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10
|
|
// CHECK13-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
|
|
// CHECK13: for.body13:
|
|
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK13-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64
|
|
// CHECK13-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]]
|
|
// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_INC16:%.*]]
|
|
// CHECK13: for.inc16:
|
|
// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK13-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK13-NEXT: store i32 [[INC17]], i32* [[I10]], align 4
|
|
// CHECK13-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK13: for.end18:
|
|
// CHECK13-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@main
|
|
// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8
|
|
// CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8
|
|
// CHECK14-NEXT: store i32 100, i32* [[N]], align 4
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
|
|
// CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK14: for.cond:
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP3]], [[TMP4]]
|
|
// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK14: for.body:
|
|
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
|
|
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM]]
|
|
// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK14: for.inc:
|
|
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
|
|
// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
|
|
// CHECK14: for.end:
|
|
// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND2:%.*]]
|
|
// CHECK14: for.cond2:
|
|
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]
|
|
// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]]
|
|
// CHECK14: for.body4:
|
|
// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64
|
|
// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM5]]
|
|
// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_INC7:%.*]]
|
|
// CHECK14: for.inc7:
|
|
// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP4:![0-9]+]]
|
|
// CHECK14: for.end9:
|
|
// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND11:%.*]]
|
|
// CHECK14: for.cond11:
|
|
// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP12]], [[TMP13]]
|
|
// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
|
|
// CHECK14: for.body13:
|
|
// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP14]] to i64
|
|
// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[IDXPROM14]]
|
|
// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_INC16:%.*]]
|
|
// CHECK14: for.inc16:
|
|
// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
|
|
// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
|
|
// CHECK14: for.end18:
|
|
// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
|
|
// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP16]])
|
|
// CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
|
|
// CHECK14-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP17]])
|
|
// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
// CHECK14-NEXT: ret i32 [[TMP18]]
|
|
//
|
|
//
|
|
// CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
|
|
// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
|
|
// CHECK14-NEXT: entry:
|
|
// CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[I1:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: [[I10:%.*]] = alloca i32, align 4
|
|
// CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK14-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK14: for.cond:
|
|
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
|
|
// CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK14: for.body:
|
|
// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
|
|
// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM]]
|
|
// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK14: for.inc:
|
|
// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
|
|
// CHECK14: for.end:
|
|
// CHECK14-NEXT: store i32 0, i32* [[I1]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND2:%.*]]
|
|
// CHECK14: for.cond2:
|
|
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK14-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10
|
|
// CHECK14-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END9:%.*]]
|
|
// CHECK14: for.body4:
|
|
// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP4]] to i64
|
|
// CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM5]]
|
|
// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_INC7:%.*]]
|
|
// CHECK14: for.inc7:
|
|
// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK14-NEXT: [[INC8:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK14-NEXT: store i32 [[INC8]], i32* [[I1]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK14: for.end9:
|
|
// CHECK14-NEXT: store i32 0, i32* [[I10]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND11:%.*]]
|
|
// CHECK14: for.cond11:
|
|
// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK14-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 10
|
|
// CHECK14-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
|
|
// CHECK14: for.body13:
|
|
// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK14-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP7]] to i64
|
|
// CHECK14-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i64 0, i64 [[IDXPROM14]]
|
|
// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX15]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_INC16:%.*]]
|
|
// CHECK14: for.inc16:
|
|
// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I10]], align 4
|
|
// CHECK14-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK14-NEXT: store i32 [[INC17]], i32* [[I10]], align 4
|
|
// CHECK14-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK14: for.end18:
|
|
// CHECK14-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@main
|
|
// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
|
|
// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 100, i32* [[N]], align 4
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK15: for.cond:
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]]
|
|
// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK15: for.body:
|
|
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]]
|
|
// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK15: for.inc:
|
|
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK15: for.end:
|
|
// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND2:%.*]]
|
|
// CHECK15: for.cond2:
|
|
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
|
|
// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]]
|
|
// CHECK15: for.body4:
|
|
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]]
|
|
// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_INC6:%.*]]
|
|
// CHECK15: for.inc6:
|
|
// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]]
|
|
// CHECK15: for.end8:
|
|
// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND10:%.*]]
|
|
// CHECK15: for.cond10:
|
|
// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]]
|
|
// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]]
|
|
// CHECK15: for.body12:
|
|
// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]]
|
|
// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_INC14:%.*]]
|
|
// CHECK15: for.inc14:
|
|
// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1
|
|
// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]
|
|
// CHECK15: for.end16:
|
|
// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
|
|
// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]])
|
|
// CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
|
|
// CHECK15-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP16]])
|
|
// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
// CHECK15-NEXT: ret i32 [[TMP17]]
|
|
//
|
|
//
|
|
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
|
|
// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
|
|
// CHECK15-NEXT: entry:
|
|
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[I1:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4
|
|
// CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK15-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK15: for.cond:
|
|
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
|
|
// CHECK15-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK15: for.body:
|
|
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]]
|
|
// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK15: for.inc:
|
|
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK15-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK15: for.end:
|
|
// CHECK15-NEXT: store i32 0, i32* [[I1]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND2:%.*]]
|
|
// CHECK15: for.cond2:
|
|
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK15-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10
|
|
// CHECK15-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]]
|
|
// CHECK15: for.body4:
|
|
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]]
|
|
// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_INC6:%.*]]
|
|
// CHECK15: for.inc6:
|
|
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK15-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK15-NEXT: store i32 [[INC7]], i32* [[I1]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK15: for.end8:
|
|
// CHECK15-NEXT: store i32 0, i32* [[I9]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND10:%.*]]
|
|
// CHECK15: for.cond10:
|
|
// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK15-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10
|
|
// CHECK15-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]]
|
|
// CHECK15: for.body12:
|
|
// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]]
|
|
// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_INC14:%.*]]
|
|
// CHECK15: for.inc14:
|
|
// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK15-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK15-NEXT: store i32 [[INC15]], i32* [[I9]], align 4
|
|
// CHECK15-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
|
|
// CHECK15: for.end16:
|
|
// CHECK15-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@main
|
|
// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4
|
|
// CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 100, i32* [[N]], align 4
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK16: for.cond:
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]]
|
|
// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK16: for.body:
|
|
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP4]]
|
|
// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK16: for.inc:
|
|
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
|
|
// CHECK16: for.end:
|
|
// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND2:%.*]]
|
|
// CHECK16: for.cond2:
|
|
// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
|
|
// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]]
|
|
// CHECK16: for.body4:
|
|
// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP8]]
|
|
// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_INC6:%.*]]
|
|
// CHECK16: for.inc6:
|
|
// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]]
|
|
// CHECK16: for.end8:
|
|
// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND10:%.*]]
|
|
// CHECK16: for.cond10:
|
|
// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[N]], align 4
|
|
// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP11]], [[TMP12]]
|
|
// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]]
|
|
// CHECK16: for.body12:
|
|
// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP13]]
|
|
// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_INC14:%.*]]
|
|
// CHECK16: for.inc14:
|
|
// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP14]], 1
|
|
// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]
|
|
// CHECK16: for.end16:
|
|
// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
|
|
// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP15]])
|
|
// CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
|
|
// CHECK16-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP16]])
|
|
// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4
|
|
// CHECK16-NEXT: ret i32 [[TMP17]]
|
|
//
|
|
//
|
|
// CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
|
|
// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
|
|
// CHECK16-NEXT: entry:
|
|
// CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[I1:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4
|
|
// CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
|
|
// CHECK16-NEXT: store i32 0, i32* [[I]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND:%.*]]
|
|
// CHECK16: for.cond:
|
|
// CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
|
|
// CHECK16-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
|
|
// CHECK16: for.body:
|
|
// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP1]]
|
|
// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_INC:%.*]]
|
|
// CHECK16: for.inc:
|
|
// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
|
|
// CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1
|
|
// CHECK16-NEXT: store i32 [[INC]], i32* [[I]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
// CHECK16: for.end:
|
|
// CHECK16-NEXT: store i32 0, i32* [[I1]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND2:%.*]]
|
|
// CHECK16: for.cond2:
|
|
// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK16-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP3]], 10
|
|
// CHECK16-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END8:%.*]]
|
|
// CHECK16: for.body4:
|
|
// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP4]]
|
|
// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX5]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_INC6:%.*]]
|
|
// CHECK16: for.inc6:
|
|
// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I1]], align 4
|
|
// CHECK16-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP5]], 1
|
|
// CHECK16-NEXT: store i32 [[INC7]], i32* [[I1]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
// CHECK16: for.end8:
|
|
// CHECK16-NEXT: store i32 0, i32* [[I9]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND10:%.*]]
|
|
// CHECK16: for.cond10:
|
|
// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK16-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP6]], 10
|
|
// CHECK16-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END16:%.*]]
|
|
// CHECK16: for.body12:
|
|
// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[A]], i32 0, i32 [[TMP7]]
|
|
// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_INC14:%.*]]
|
|
// CHECK16: for.inc14:
|
|
// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I9]], align 4
|
|
// CHECK16-NEXT: [[INC15:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK16-NEXT: store i32 [[INC15]], i32* [[I9]], align 4
|
|
// CHECK16-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
|
|
// CHECK16: for.end16:
|
|
// CHECK16-NEXT: ret i32 0
|
|
//
|