| .. |
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intrinsics
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[Hexagon] Add support for __builtin_prefetch
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2016-02-18 13:58:38 +00:00 |
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vect
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[Hexagon] Split double registers
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2015-10-16 20:38:54 +00:00 |
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Atomics.ll
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[Hexagon] Handle expansion of cmpxchg
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2016-06-22 16:07:10 +00:00 |
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BranchPredict.ll
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[Hexagon] Some cleanup of instruction selection code
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2015-04-22 21:17:00 +00:00 |
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NVJumpCmp.ll
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[Hexagon] Add NewValueJump support for C4_cmpneq, C4_cmplte, C4_cmplteu
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2015-12-08 16:28:32 +00:00 |
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absaddr-store.ll
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[Hexagon] Fix printing the address operand of S2_storerinewabs
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2016-04-19 20:20:33 +00:00 |
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absimm.ll
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[Hexagon] Fixing store instructions and reenabling a few more tests.
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2015-11-10 00:22:00 +00:00 |
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adde.ll
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[Hexagon] Enable the post-RA scheduler
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2016-05-26 19:44:28 +00:00 |
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addh-sext-trunc.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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addh-shifted.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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addh.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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addrmode-indoff.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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alu64.ll
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[Hexagon] Preprocess mapped instructions before lowering to MC
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2015-12-15 17:05:45 +00:00 |
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always-ext.ll
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[Hexagon] Fixing load instruction parsing and reenabling tests.
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2015-11-10 00:02:27 +00:00 |
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args.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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ashift-left-right.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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avoid-predspill-calleesaved.ll
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[Hexagon] Optimize stack slot spills
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2016-02-12 22:53:35 +00:00 |
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avoid-predspill.ll
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[Hexagon] Optimize stack slot spills
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2016-02-12 22:53:35 +00:00 |
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barrier-flag.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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base-offset-addr.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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base-offset-post.ll
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[Hexagon] Adding some codegen tests and updating some to match spec.
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2015-06-13 21:46:39 +00:00 |
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bit-eval.ll
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[Hexagon] Preprocess mapped instructions before lowering to MC
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2015-12-15 17:05:45 +00:00 |
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bit-extractu-half.ll
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[Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword
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2016-01-14 21:59:22 +00:00 |
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bit-loop.ll
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[Hexagon] Bit-based instruction simplification
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2015-10-20 22:57:13 +00:00 |
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bit-phi.ll
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[Hexagon] Do not insert non-phis before phis in bit simplification
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2016-01-13 15:48:18 +00:00 |
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bitconvert-vector.ll
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[Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)
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2016-06-27 15:08:22 +00:00 |
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block-addr.ll
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[Hexagon] Treat all conditional branches as predicted (not-taken by default)
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2016-05-09 18:22:07 +00:00 |
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block-ranges-nodef.ll
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[Hexagon] Properly close live range in HexagonBlockRanges ---add testcase
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2016-04-22 17:30:13 +00:00 |
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branch-non-mbb.ll
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[Hexagon] Handle branches with non-mbb operands
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2016-01-14 15:05:27 +00:00 |
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brev_ld.ll
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[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
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2016-02-12 17:01:51 +00:00 |
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brev_st.ll
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[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
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2016-02-12 17:01:51 +00:00 |
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bugAsmHWloop.ll
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[Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets.
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2015-06-18 20:43:50 +00:00 |
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builtin-prefetch-offset.ll
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[Hexagon] Add support for __builtin_prefetch
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2016-02-18 13:58:38 +00:00 |
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builtin-prefetch.ll
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[Hexagon] Add support for __builtin_prefetch
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2016-02-18 13:58:38 +00:00 |
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calling-conv-2.ll
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[PATCH] [HEXAGON] Add a test program to verify calling convention
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2015-05-12 20:13:10 +00:00 |
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callr-dep-edge.ll
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[ScheduleDAG] Make sure to process all def operands before any use operands
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2016-05-10 16:50:30 +00:00 |
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cext-check.ll
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[Hexagon] Simplify HexagonInstrInfo::isPredicable
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2016-05-16 16:56:10 +00:00 |
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cext-valid-packet1.ll
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[Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets.
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2015-06-18 20:43:50 +00:00 |
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cext-valid-packet2.ll
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[Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets.
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2015-06-18 20:43:50 +00:00 |
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cext.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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cexti16.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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cfi-late.ll
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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cfi-offset.ll
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[Hexagon] Use offsets relative to FP+8 in .cfi_offset instructions
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2016-05-11 14:53:07 +00:00 |
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checktabs.ll
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[Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets.
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2015-06-18 20:43:50 +00:00 |
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circ-load-isel.ll
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[Hexagon] Remove dead nodes from SelectionDAG to avoid cycles
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2016-05-13 18:48:15 +00:00 |
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circ_ld.ll
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[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
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2016-02-12 17:01:51 +00:00 |
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circ_ldd_bug.ll
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[Hexagon] Intrinsics for circular and bit-reversed loads and stores
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2015-03-18 16:23:44 +00:00 |
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circ_ldw.ll
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[Hexagon] Intrinsics for circular and bit-reversed loads and stores
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2015-03-18 16:23:44 +00:00 |
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circ_st.ll
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[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
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2016-02-12 17:01:51 +00:00 |
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clr_set_toggle.ll
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[Hexagon] Bit-based instruction simplification
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2015-10-20 22:57:13 +00:00 |
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cmp-extend.ll
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[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
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2015-06-17 17:19:05 +00:00 |
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cmp-promote.ll
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[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
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2015-06-17 17:19:05 +00:00 |
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cmp-to-genreg.ll
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[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
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2015-06-17 17:19:05 +00:00 |
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cmp-to-predreg.ll
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[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
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2015-06-17 17:19:05 +00:00 |
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cmp.ll
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Revert r265817
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2016-04-08 18:15:37 +00:00 |
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cmp_pred.ll
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[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
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2015-06-17 17:19:05 +00:00 |
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cmp_pred2.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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cmp_pred_reg.ll
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[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
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2015-06-17 17:19:05 +00:00 |
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cmpb-eq.ll
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[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
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2015-06-17 17:19:05 +00:00 |
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cmpb_pred.ll
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[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
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2015-06-17 17:19:05 +00:00 |
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combine.ll
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[Hexagon] Split double registers
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2015-10-16 20:38:54 +00:00 |
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combine_ir.ll
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[Hexagon] Split double registers
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2015-10-16 20:38:54 +00:00 |
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common-gep-basic.ll
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[Hexagon] Implement commoning of GetElementPtr instructions
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2015-07-08 19:22:28 +00:00 |
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common-gep-icm.ll
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[Hexagon] Implement commoning of GetElementPtr instructions
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2015-07-08 19:22:28 +00:00 |
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compound.ll
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[Hexagon] Fixing compound register printing and reenabling more tests.
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2015-11-10 00:51:56 +00:00 |
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const64.ll
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[Hexagon] Generate CONST64 when optimizing for size in copy-to-combine
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2016-01-15 14:08:31 +00:00 |
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convertdptoint.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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convertdptoll.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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convertsptoint.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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convertsptoll.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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csr-func-usedef.ll
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[Hexagon] Register save/restore functions do not follow regular conventions
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2016-04-25 17:49:44 +00:00 |
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ctlz-cttz-ctpop.ll
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[Hexagon] Some cleanup of instruction selection code
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2015-04-22 21:17:00 +00:00 |
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ctor.ll
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Handle ctor/init_array initialization.
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2014-11-03 14:56:05 +00:00 |
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dadd.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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dmul.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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double.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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doubleconvert-ieee-rnd-near.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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dsub.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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dualstore.ll
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[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
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2015-06-05 16:00:11 +00:00 |
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duplex.ll
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[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
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2015-06-05 16:00:11 +00:00 |
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early-if-conversion-bug1.ll
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[Hexagon] Add an early if-conversion pass
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2015-10-06 15:49:14 +00:00 |
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early-if-phi-i1.ll
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[Hexagon] Add an early if-conversion pass
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2015-10-06 15:49:14 +00:00 |
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early-if-spare.ll
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[Hexagon] Add an early if-conversion pass
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2015-10-06 15:49:14 +00:00 |
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early-if.ll
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[Hexagon] Add an early if-conversion pass
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2015-10-06 15:49:14 +00:00 |
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eh_return.ll
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[Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets.
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2015-06-18 20:43:50 +00:00 |
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eliminate-pred-spill.ll
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[Hexagon] Optimize stack slot spills
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2016-02-12 22:53:35 +00:00 |
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expand-condsets-basic.ll
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Expand MUX instructions early on Hexagon
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2015-03-31 13:35:12 +00:00 |
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expand-condsets-pred-undef.ll
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[Hexagon] Teach mux expansion how to deal with undef predicates
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2016-04-22 16:47:01 +00:00 |
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expand-condsets-rm-segment.ll
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Expand MUX instructions early on Hexagon
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2015-03-31 13:35:12 +00:00 |
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expand-condsets-undef.ll
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Expand MUX instructions early on Hexagon
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2015-03-31 13:35:12 +00:00 |
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extload-combine.ll
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[Hexagon] Expand handling of the small-data/bss section
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2016-04-21 18:56:45 +00:00 |
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extract-basic.ll
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[Hexagon] Generate "extract" instructions more aggressively
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2015-07-14 17:07:24 +00:00 |
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fadd.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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fcmp.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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float.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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floatconvert-ieee-rnd-near.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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fmul.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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frame.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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fsub.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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fusedandshift.ll
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[Hexagon] Generate "extract" instructions more aggressively
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2015-07-14 17:07:24 +00:00 |
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gp-plus-offset-load.ll
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[Hexagon] Missed testcase update in r260895
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2016-02-15 16:15:02 +00:00 |
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gp-plus-offset-store.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to gep operator
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2015-03-13 18:20:45 +00:00 |
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gp-rel.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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hwloop-cleanup.ll
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[Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranch
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2015-03-18 15:56:43 +00:00 |
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hwloop-const.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
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2015-02-27 19:29:02 +00:00 |
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hwloop-crit-edge.ll
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[Hexagon] Generate hardware loop when loop has a critical edge
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2015-05-13 14:54:24 +00:00 |
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hwloop-dbg.ll
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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hwloop-le.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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hwloop-loop1.ll
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[Hexagon] Generate loop1 instruction for nested loops
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2015-05-13 17:56:03 +00:00 |
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hwloop-lt.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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hwloop-lt1.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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hwloop-missed.ll
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[Hexagon] Generate more hardware loops
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2015-05-08 20:18:21 +00:00 |
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hwloop-ne.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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hwloop-ph-deadcode.ll
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[Hexagon] Remove dead constant assignment in hardware loop pass
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2015-05-14 17:31:40 +00:00 |
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hwloop-pos-ivbump1.ll
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[Hexagon] Check for underflow/wrap in hardware loop pass
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2015-05-14 14:15:08 +00:00 |
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hwloop-preheader.ll
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[Hexagon] Generate more hardware loops
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2015-05-08 20:18:21 +00:00 |
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hwloop-range.ll
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[Hexagon] Use constant extenders to fix up hardware loops
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2015-04-27 14:16:43 +00:00 |
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hwloop-recursion.ll
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[Hexagon] Check for underflow/wrap in hardware loop pass
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2015-05-14 14:15:08 +00:00 |
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hwloop-wrap.ll
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[Hexagon] Check for underflow/wrap in hardware loop pass
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2015-05-14 14:15:08 +00:00 |
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hwloop-wrap2.ll
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[Hexagon] Check for underflow/wrap in hardware loop pass
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2015-05-14 14:15:08 +00:00 |
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hwloop1.ll
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[Hexagon] Generate more hardware loops
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2015-05-08 20:18:21 +00:00 |
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hwloop2.ll
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[Hexagon] Generate more hardware loops
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2015-05-08 20:18:21 +00:00 |
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hwloop3.ll
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[Hexagon] Generate more hardware loops
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2015-05-08 20:18:21 +00:00 |
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hwloop4.ll
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[Hexagon] Generate more hardware loops
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2015-05-08 20:18:21 +00:00 |
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hwloop5.ll
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[Hexagon] Generate hardware loop for a vectorized loop
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2015-05-14 20:36:19 +00:00 |
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i1_VarArg.ll
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Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
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2015-11-25 20:30:59 +00:00 |
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i8_VarArg.ll
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Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
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2015-11-25 20:30:59 +00:00 |
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i16_VarArg.ll
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Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
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2015-11-25 20:30:59 +00:00 |
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idxload-with-zero-offset.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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ifcvt-diamond-bad.ll
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Proper handling of diamond-like cases in if-conversion
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2016-01-20 13:14:52 +00:00 |
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ifcvt-edge-weight.ll
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Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
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2015-12-01 05:29:22 +00:00 |
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indirect-br.ll
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…
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inline-asm-qv.ll
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[Hexagon] Recognize "q" and "v" in inline-asm as register constraints
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2016-05-18 14:34:51 +00:00 |
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insert-basic.ll
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[Hexagon] Generate "insert" instructions more aggressively
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2015-07-08 14:47:34 +00:00 |
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insert4.ll
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[Hexagon] Expand pseudo instruction Insert4
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2016-01-14 15:37:16 +00:00 |
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lit.local.cfg
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…
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loadi1-G0.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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loadi1-v4-G0.ll
|
[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
|
2015-06-17 20:29:33 +00:00 |
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loadi1-v4.ll
|
[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
|
2015-06-17 20:29:33 +00:00 |
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loadi1.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
|
2015-06-17 20:29:33 +00:00 |
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macint.ll
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[Hexagon] Some cleanup of instruction selection code
|
2015-04-22 21:17:00 +00:00 |
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maxd.ll
|
[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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maxh.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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maxud.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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maxuw.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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maxw.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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mem-fi-add.ll
|
Revert "Change memcpy/memset/memmove to have dest and source alignments."
|
2015-11-19 05:56:52 +00:00 |
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memcpy-likely-aligned.ll
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[Hexagon] Make memcpy lowering thread-safe
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2015-12-16 17:29:37 +00:00 |
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memops.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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memops1.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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memops2.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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memops3.ll
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[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
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2015-02-27 21:17:42 +00:00 |
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mind.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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minu-zext-8.ll
|
[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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minu-zext-16.ll
|
[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
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2015-06-17 20:29:33 +00:00 |
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minud.ll
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[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
|
2015-06-17 20:29:33 +00:00 |
|
minuw.ll
|
[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
|
2015-06-17 20:29:33 +00:00 |
|
minw.ll
|
[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
|
2015-06-17 20:29:33 +00:00 |
|
misaligned-access.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
misched-top-rptracker-sync.ll
|
Reset the TopRPTracker's position in ScheduleDAGMILive::initQueues
|
2016-04-28 19:17:44 +00:00 |
|
mpy.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
mux-basic.ll
|
[Hexagon] Generate MUX from conditional transfers when dot-new not possible
|
2015-07-20 21:23:25 +00:00 |
|
newvaluejump.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
newvaluejump2.ll
|
[Hexagon] Some cleanup of instruction selection code
|
2015-04-22 21:17:00 +00:00 |
|
newvaluestore.ll
|
[Hexagon] Enable the post-RA scheduler
|
2016-05-26 19:44:28 +00:00 |
|
opt-addr-mode.ll
|
[Hexagon] Optimize addressing modes for load/store
|
2016-04-29 15:49:13 +00:00 |
|
opt-fabs.ll
|
[Hexagon] Bit-based instruction simplification
|
2015-10-20 22:57:13 +00:00 |
|
opt-fneg.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
packetize_cond_inst.ll
|
…
|
|
|
peephole-op-swap.ll
|
[Hexagon] Fix operand swapping in HexagonPeephole
|
2016-04-19 21:36:24 +00:00 |
|
pic-jumptables.ll
|
[Hexagon] Add PIC support
|
2015-12-18 20:19:30 +00:00 |
|
pic-local.ll
|
Start using shouldAssumeDSOLocal on Hexagon.
|
2016-06-22 19:09:14 +00:00 |
|
pic-regusage.ll
|
[Hexagon] Generate PIC-specific versions of save/restore routines
|
2016-03-24 19:18:48 +00:00 |
|
pic-simple.ll
|
[Hexagon] Add PIC support
|
2015-12-18 20:19:30 +00:00 |
|
pic-static.ll
|
[Hexagon] Add PIC support
|
2015-12-18 20:19:30 +00:00 |
|
postinc-load.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
postinc-offset.ll
|
[Hexagon] Implement RDF-based post-RA optimizations
|
2016-01-12 19:09:01 +00:00 |
|
postinc-store.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
pred-absolute-store.ll
|
[Hexagon] Removing unused patterns.
|
2015-03-09 23:08:46 +00:00 |
|
pred-gp.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
pred-instrs.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
predicate-copy.ll
|
…
|
|
|
predicate-logical.ll
|
[Hexagon] Generate instructions for operations on predicate registers
|
2015-07-14 19:30:21 +00:00 |
|
predicate-rcmp.ll
|
[Hexagon] Generate instructions for operations on predicate registers
|
2015-07-14 19:30:21 +00:00 |
|
rdf-copy-undef2.ll
|
[RDF] Handle undefined registers in RDF copy propagation
|
2016-04-28 15:09:19 +00:00 |
|
rdf-copy.ll
|
Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT.
|
2016-02-26 19:40:34 +00:00 |
|
rdf-dead-loop.ll
|
[Hexagon] Implement RDF-based post-RA optimizations
|
2016-01-12 19:09:01 +00:00 |
|
rdf-inline-asm-fixed.ll
|
[RDF] Improve handling of inline-asm
|
2016-04-28 20:33:33 +00:00 |
|
rdf-inline-asm.ll
|
[RDF] Improve handling of inline-asm
|
2016-04-28 20:33:33 +00:00 |
|
rdf-reset-kills.ll
|
[RDF] Consider register as live if any alias is live
|
2016-04-20 14:33:23 +00:00 |
|
reg-scavengebug-3.ll
|
[Hexagon] Optimize stack slot spills
|
2016-02-12 22:53:35 +00:00 |
|
reg-scavenger-valid-slot.ll
|
When looking for a spill slot in reg scavenger, find one that matches RC
|
2016-05-18 18:16:00 +00:00 |
|
relax.ll
|
Revert r265817
|
2016-04-08 18:15:37 +00:00 |
|
remove-endloop.ll
|
[Hexagon] Update AnalyzeBranch, etc target hooks
|
2015-05-08 16:16:29 +00:00 |
|
remove_lsr.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
restore-single-reg.ll
|
[Hexagon] Only use restore functions for single register at -Oz
|
2016-03-28 14:52:21 +00:00 |
|
runtime-stkchk.ll
|
[Hexagon] Add support for run-time stack overflow checking
|
2016-03-24 20:20:07 +00:00 |
|
sdata-array.ll
|
[Hexagon] Expand handling of the small-data/bss section
|
2016-04-21 18:56:45 +00:00 |
|
sdata-basic.ll
|
[Hexagon] Expand handling of the small-data/bss section
|
2016-04-21 18:56:45 +00:00 |
|
sdr-basic.ll
|
[Hexagon] Split double registers
|
2015-10-16 20:38:54 +00:00 |
|
sdr-shr32.ll
|
[Hexagon] Split double registers
|
2015-10-16 20:38:54 +00:00 |
|
section_7275.ll
|
[Hexagon] Expand handling of the small-data/bss section
|
2016-04-21 18:56:45 +00:00 |
|
select-instr-align.ll
|
[Hexagon] Improve handling of unaligned vector loads and stores
|
2016-03-28 15:43:03 +00:00 |
|
shrink-frame-basic.ll
|
[Hexagon] Shrink-wrap stack frame (Hexagon-specific)
|
2015-04-23 16:05:39 +00:00 |
|
signed_immediates.ll
|
[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
|
2015-06-10 16:52:32 +00:00 |
|
simple_addend.ll
|
[Hexagon] Delay emission of CFI instructions
|
2015-10-19 17:46:01 +00:00 |
|
simpletailcall.ll
|
…
|
|
|
split-const32-const64.ll
|
…
|
|
|
stack-align1.ll
|
[Hexagon] Add testcases for stack alignment and variable-sized objects
|
2015-04-23 15:12:49 +00:00 |
|
stack-align2.ll
|
[Hexagon] Add testcases for stack alignment and variable-sized objects
|
2015-04-23 15:12:49 +00:00 |
|
stack-alloca1.ll
|
[Hexagon] Add testcases for stack alignment and variable-sized objects
|
2015-04-23 15:12:49 +00:00 |
|
stack-alloca2.ll
|
[Hexagon] Add testcases for stack alignment and variable-sized objects
|
2015-04-23 15:12:49 +00:00 |
|
static.ll
|
[Hexagon] Expand handling of the small-data/bss section
|
2016-04-21 18:56:45 +00:00 |
|
store-shift.ll
|
[Hexagon] Add SDAG preprocessing step to expose shifted addressing modes
|
2016-06-22 20:08:27 +00:00 |
|
store-widen-aliased-load.ll
|
[Hexagon] Merge adjacent stores
|
2015-10-16 19:43:56 +00:00 |
|
store-widen-negv.ll
|
[Hexagon] Merge adjacent stores
|
2015-10-16 19:43:56 +00:00 |
|
store-widen-negv2.ll
|
[Hexagon] Merge adjacent stores
|
2015-10-16 19:43:56 +00:00 |
|
store-widen.ll
|
[Hexagon] Merge adjacent stores
|
2015-10-16 19:43:56 +00:00 |
|
storerinewabs.ll
|
[Hexagon] Fix printing the address operand of S2_storerinewabs
|
2016-04-19 20:20:33 +00:00 |
|
struct_args.ll
|
[Hexagon] Split double registers
|
2015-10-16 20:38:54 +00:00 |
|
struct_args_large.ll
|
The canonical way to XFAIL a test for all targets is XFAIL: *, not XFAIL:
|
2016-02-04 16:21:38 +00:00 |
|
sube.ll
|
[Hexagon] Enable the post-RA scheduler
|
2016-05-26 19:44:28 +00:00 |
|
tail-call-mem-intrinsics.ll
|
Revert "Change memcpy/memset/memmove to have dest and source alignments."
|
2015-11-19 05:56:52 +00:00 |
|
tail-call-trunc.ll
|
…
|
|
|
tail-dup-subreg-abort.ll
|
Tail duplication can mix incompatible registers in phi nodes
|
2015-10-21 02:40:06 +00:00 |
|
tail-dup-subreg-map.ll
|
[Tail duplication] Handle source registers with subregisters
|
2016-04-26 18:36:34 +00:00 |
|
tfr-to-combine.ll
|
[Hexagon] Split double registers
|
2015-10-16 20:38:54 +00:00 |
|
tls_pic.ll
|
[Hexagon] Optimize addressing modes for load/store
|
2016-04-29 15:49:13 +00:00 |
|
tls_static.ll
|
[Hexagon] Optimize addressing modes for load/store
|
2016-04-29 15:49:13 +00:00 |
|
union-1.ll
|
[Hexagon] Split double registers
|
2015-10-16 20:38:54 +00:00 |
|
usr-ovf-dep.ll
|
[Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets.
|
2015-06-18 20:43:50 +00:00 |
|
v60Intrins.ll
|
[Hexagon] Enable the post-RA scheduler
|
2016-05-26 19:44:28 +00:00 |
|
v60Vasr.ll
|
[Hexagon] Adding v60 test, vasr in particular.
|
2015-12-07 18:52:39 +00:00 |
|
v60small.ll
|
[Hexagon] Hexagon V60 HVX intrinsic defintions
|
2015-11-26 16:54:33 +00:00 |
|
vaddh.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
validate-offset.ll
|
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
|
2015-02-27 21:17:42 +00:00 |
|
vec-pred-spill1.ll
|
[Hexagon] Optimize stack slot spills
|
2016-02-12 22:53:35 +00:00 |
|
vector-align.ll
|
[Hexagon] Specify vector alignment in DataLayout string
|
2016-02-12 14:47:38 +00:00 |
|
vload-postinc-sel.ll
|
[Hexagon] Simplify (+fix) instruction selection for indexed loads/stores
|
2016-06-24 21:27:17 +00:00 |
|
vselect-pseudo.ll
|
[Hexagon] Expand VSelect pseudo instructions
|
2016-05-12 19:16:02 +00:00 |
|
vsplat-isel.ll
|
[Hexagon] Properly handle instruction selection of vsplat intrinsics
|
2016-05-12 17:21:40 +00:00 |
|
zextloadi1.ll
|
[Hexagon] Optimize addressing modes for load/store
|
2016-04-29 15:49:13 +00:00 |
5da24e5495