forked from OSchip/llvm-project
124 lines
4.3 KiB
ArmAsm
124 lines
4.3 KiB
ArmAsm
// REQUIRES: arm
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// RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf --arm-add-build-attributes %s -o %t.o
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// RUN: ld.lld --fix-cortex-a8 -verbose %t.o -o %t2
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// RUN: llvm-objdump -d %t2 --start-address=0x21ffa --stop-address=0x22002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE1 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x22ffa --stop-address=0x23002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE2 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x23ffa --stop-address=0x24002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE3 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x24ffa --stop-address=0x25006 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE4 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x25ffe --stop-address=0x26002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE5 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x27000 --stop-address=0x28004 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE6 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x28002 --stop-address=0x29006 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE7 %s
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/// Test boundary conditions of the cortex-a8 erratum. The following cases
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/// should not trigger the Erratum
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.syntax unified
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.thumb
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.text
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.global _start
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.balign 4096
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.thumb_func
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_start:
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nop.w
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.space 4086
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.thumb_func
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target:
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/// 32-bit branch spans 2 4KiB regions, preceded by a 32-bit branch so no patch
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/// expected.
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b.w target
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b.w target
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// CALLSITE1: 00021ffa <target>:
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// CALLSITE1-NEXT: 21ffa: b.w #-4
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// CALLSITE1-NEXT: 21ffe: b.w #-8
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.space 4088
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.type target2, %function
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target2:
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/// 32-bit Branch and link spans 2 4KiB regions, preceded by a 16-bit
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/// instruction so no patch expected.
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nop
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nop
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bl target2
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// CALLSITE2: 00022ffa <target2>:
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// CALLSITE2-NEXT: 22ffa: nop
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// CALLSITE2-NEXT: 22ffc: nop
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// CALLSITE2-NEXT: 22ffe: bl #-8
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.space 4088
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.type target3, %function
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target3:
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/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, branch is backwards but outside 4KiB region. So
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/// expect no patch.
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nop.w
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beq.w target2
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// CALLSITE3: 00023ffa <target3>:
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// CALLSITE3-NEXT: 23ffa: nop.w
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// CALLSITE3-NEXT: 23ffe: beq.w #-4104
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.space 4088
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.type source4, %function
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source4:
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/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, branch is forwards to 2nd region so expect no patch.
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nop.w
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beq.w target4
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.thumb_func
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target4:
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nop.w
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// CALLSITE4: 00024ffa <source4>:
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// CALLSITE4-NEXT: 24ffa: nop.w
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// CALLSITE4-NEXT: 24ffe: beq.w #0
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// CALLSITE4: 00025002 <target4>:
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// CALLSITE4-NEXT: 25002: nop.w
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.space 4084
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.type target5, %function
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target5:
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/// 32-bit conditional branch spans 2 4KiB regions, preceded by the encoding of
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/// a 32-bit thumb instruction, but in ARM state (illegal instruction), we
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/// should not decode and match it as Thumb, expect no patch.
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.arm
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.inst 0x800f3af /// nop.w encoding in Thumb
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.thumb
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.thumb_func
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source5:
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beq.w target5
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// CALLSITE5: 00025ffe <source5>:
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// CALLSITE5-NEXT: 25ffe: beq.w #-8
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/// Edge case where two word sequence starts at offset 0xffc, check that
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/// we don't match. In this case the branch will be completely in the 2nd
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/// region and the branch will target the second region. This will pass a
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/// branch destination in the same region test, but not the branch must have
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/// and address of the form xxxxxffe.
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.space 4090
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.type target6, %function
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nop.w
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/// Make sure target of branch is in the same 4KiB region as the branch.
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target6:
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bl target6
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// CALLSITE6: 00027000 <target6>:
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// CALLSITE6-NEXT: 27000: bl #-4
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/// Edge case where two word sequence starts at offset 0xffe, check that
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/// we don't match. In this case the branch will be completely in the 2nd
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/// region and the branch will target the second region. This will pass a
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/// branch destination in the same region test, but not the branch must have
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/// and address of the form xxxxxffe.
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.space 4090
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.type target7, %function
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nop.w
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/// Make sure target of branch is in the same 4KiB region as the branch.
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target7:
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bl target7
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// CALLSITE7: 00028002 <target7>:
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// CALLSITE7: 28002: bl #-4
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