forked from OSchip/llvm-project
272 lines
9.8 KiB
C++
272 lines
9.8 KiB
C++
//===- IndirectBrExpandPass.cpp - Expand indirectbr to switch -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// Implements an expansion pass to turn `indirectbr` instructions in the IR
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/// into `switch` instructions. This works by enumerating the basic blocks in
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/// a dense range of integers, replacing each `blockaddr` constant with the
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/// corresponding integer constant, and then building a switch that maps from
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/// the integers to the actual blocks. All of the indirectbr instructions in the
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/// function are redirected to this common switch.
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///
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/// While this is generically useful if a target is unable to codegen
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/// `indirectbr` natively, it is primarily useful when there is some desire to
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/// get the builtin non-jump-table lowering of a switch even when the input
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/// source contained an explicit indirect branch construct.
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///
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/// Note that it doesn't make any sense to enable this pass unless a target also
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/// disables jump-table lowering of switches. Doing that is likely to pessimize
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/// the code.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Sequence.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/DomTreeUpdater.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstIterator.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "indirectbr-expand"
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namespace {
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class IndirectBrExpandPass : public FunctionPass {
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const TargetLowering *TLI = nullptr;
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public:
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static char ID; // Pass identification, replacement for typeid
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IndirectBrExpandPass() : FunctionPass(ID) {
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initializeIndirectBrExpandPassPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addPreserved<DominatorTreeWrapperPass>();
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}
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bool runOnFunction(Function &F) override;
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};
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} // end anonymous namespace
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char IndirectBrExpandPass::ID = 0;
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INITIALIZE_PASS_BEGIN(IndirectBrExpandPass, DEBUG_TYPE,
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"Expand indirectbr instructions", false, false)
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INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
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INITIALIZE_PASS_END(IndirectBrExpandPass, DEBUG_TYPE,
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"Expand indirectbr instructions", false, false)
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FunctionPass *llvm::createIndirectBrExpandPass() {
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return new IndirectBrExpandPass();
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}
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bool IndirectBrExpandPass::runOnFunction(Function &F) {
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auto &DL = F.getParent()->getDataLayout();
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auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
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if (!TPC)
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return false;
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auto &TM = TPC->getTM<TargetMachine>();
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auto &STI = *TM.getSubtargetImpl(F);
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if (!STI.enableIndirectBrExpand())
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return false;
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TLI = STI.getTargetLowering();
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Optional<DomTreeUpdater> DTU;
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if (auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>())
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DTU.emplace(DTWP->getDomTree(), DomTreeUpdater::UpdateStrategy::Lazy);
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SmallVector<IndirectBrInst *, 1> IndirectBrs;
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// Set of all potential successors for indirectbr instructions.
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SmallPtrSet<BasicBlock *, 4> IndirectBrSuccs;
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// Build a list of indirectbrs that we want to rewrite.
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for (BasicBlock &BB : F)
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if (auto *IBr = dyn_cast<IndirectBrInst>(BB.getTerminator())) {
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// Handle the degenerate case of no successors by replacing the indirectbr
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// with unreachable as there is no successor available.
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if (IBr->getNumSuccessors() == 0) {
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(void)new UnreachableInst(F.getContext(), IBr);
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IBr->eraseFromParent();
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continue;
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}
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IndirectBrs.push_back(IBr);
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for (BasicBlock *SuccBB : IBr->successors())
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IndirectBrSuccs.insert(SuccBB);
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}
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if (IndirectBrs.empty())
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return false;
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// If we need to replace any indirectbrs we need to establish integer
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// constants that will correspond to each of the basic blocks in the function
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// whose address escapes. We do that here and rewrite all the blockaddress
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// constants to just be those integer constants cast to a pointer type.
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SmallVector<BasicBlock *, 4> BBs;
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for (BasicBlock &BB : F) {
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// Skip blocks that aren't successors to an indirectbr we're going to
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// rewrite.
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if (!IndirectBrSuccs.count(&BB))
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continue;
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auto IsBlockAddressUse = [&](const Use &U) {
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return isa<BlockAddress>(U.getUser());
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};
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auto BlockAddressUseIt = llvm::find_if(BB.uses(), IsBlockAddressUse);
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if (BlockAddressUseIt == BB.use_end())
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continue;
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assert(std::find_if(std::next(BlockAddressUseIt), BB.use_end(),
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IsBlockAddressUse) == BB.use_end() &&
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"There should only ever be a single blockaddress use because it is "
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"a constant and should be uniqued.");
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auto *BA = cast<BlockAddress>(BlockAddressUseIt->getUser());
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// Skip if the constant was formed but ended up not being used (due to DCE
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// or whatever).
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if (!BA->isConstantUsed())
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continue;
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// Compute the index we want to use for this basic block. We can't use zero
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// because null can be compared with block addresses.
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int BBIndex = BBs.size() + 1;
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BBs.push_back(&BB);
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auto *ITy = cast<IntegerType>(DL.getIntPtrType(BA->getType()));
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ConstantInt *BBIndexC = ConstantInt::get(ITy, BBIndex);
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// Now rewrite the blockaddress to an integer constant based on the index.
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// FIXME: This part doesn't properly recognize other uses of blockaddress
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// expressions, for instance, where they are used to pass labels to
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// asm-goto. This part of the pass needs a rework.
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BA->replaceAllUsesWith(ConstantExpr::getIntToPtr(BBIndexC, BA->getType()));
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}
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if (BBs.empty()) {
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// There are no blocks whose address is taken, so any indirectbr instruction
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// cannot get a valid input and we can replace all of them with unreachable.
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SmallVector<DominatorTree::UpdateType, 8> Updates;
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if (DTU)
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Updates.reserve(IndirectBrSuccs.size());
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for (auto *IBr : IndirectBrs) {
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if (DTU) {
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for (BasicBlock *SuccBB : IBr->successors())
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Updates.push_back({DominatorTree::Delete, IBr->getParent(), SuccBB});
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}
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(void)new UnreachableInst(F.getContext(), IBr);
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IBr->eraseFromParent();
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}
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if (DTU) {
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assert(Updates.size() == IndirectBrSuccs.size() &&
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"Got unexpected update count.");
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DTU->applyUpdates(Updates);
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}
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return true;
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}
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BasicBlock *SwitchBB;
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Value *SwitchValue;
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// Compute a common integer type across all the indirectbr instructions.
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IntegerType *CommonITy = nullptr;
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for (auto *IBr : IndirectBrs) {
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auto *ITy =
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cast<IntegerType>(DL.getIntPtrType(IBr->getAddress()->getType()));
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if (!CommonITy || ITy->getBitWidth() > CommonITy->getBitWidth())
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CommonITy = ITy;
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}
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auto GetSwitchValue = [DL, CommonITy](IndirectBrInst *IBr) {
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return CastInst::CreatePointerCast(
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IBr->getAddress(), CommonITy,
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Twine(IBr->getAddress()->getName()) + ".switch_cast", IBr);
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};
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SmallVector<DominatorTree::UpdateType, 8> Updates;
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if (IndirectBrs.size() == 1) {
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// If we only have one indirectbr, we can just directly replace it within
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// its block.
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IndirectBrInst *IBr = IndirectBrs[0];
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SwitchBB = IBr->getParent();
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SwitchValue = GetSwitchValue(IBr);
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if (DTU) {
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Updates.reserve(IndirectBrSuccs.size());
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for (BasicBlock *SuccBB : IBr->successors())
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Updates.push_back({DominatorTree::Delete, IBr->getParent(), SuccBB});
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assert(Updates.size() == IndirectBrSuccs.size() &&
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"Got unexpected update count.");
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}
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IBr->eraseFromParent();
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} else {
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// Otherwise we need to create a new block to hold the switch across BBs,
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// jump to that block instead of each indirectbr, and phi together the
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// values for the switch.
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SwitchBB = BasicBlock::Create(F.getContext(), "switch_bb", &F);
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auto *SwitchPN = PHINode::Create(CommonITy, IndirectBrs.size(),
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"switch_value_phi", SwitchBB);
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SwitchValue = SwitchPN;
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// Now replace the indirectbr instructions with direct branches to the
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// switch block and fill out the PHI operands.
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if (DTU)
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Updates.reserve(IndirectBrs.size() + 2 * IndirectBrSuccs.size());
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for (auto *IBr : IndirectBrs) {
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SwitchPN->addIncoming(GetSwitchValue(IBr), IBr->getParent());
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BranchInst::Create(SwitchBB, IBr);
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if (DTU) {
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Updates.push_back({DominatorTree::Insert, IBr->getParent(), SwitchBB});
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for (BasicBlock *SuccBB : IBr->successors())
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Updates.push_back({DominatorTree::Delete, IBr->getParent(), SuccBB});
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}
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IBr->eraseFromParent();
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}
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}
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// Now build the switch in the block. The block will have no terminator
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// already.
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auto *SI = SwitchInst::Create(SwitchValue, BBs[0], BBs.size(), SwitchBB);
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// Add a case for each block.
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for (int i : llvm::seq<int>(1, BBs.size()))
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SI->addCase(ConstantInt::get(CommonITy, i + 1), BBs[i]);
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if (DTU) {
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// If there were multiple indirectbr's, they may have common successors,
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// but in the dominator tree, we only track unique edges.
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SmallPtrSet<BasicBlock *, 8> UniqueSuccessors(BBs.begin(), BBs.end());
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Updates.reserve(Updates.size() + UniqueSuccessors.size());
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for (BasicBlock *BB : UniqueSuccessors)
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Updates.push_back({DominatorTree::Insert, SwitchBB, BB});
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DTU->applyUpdates(Updates);
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}
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return true;
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}
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