forked from OSchip/llvm-project
50 lines
1.9 KiB
LLVM
50 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
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; CHECK: psubw
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; CHECK-NEXT: pmullw
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; Widen a v5i16 to v8i16 to do a vector sub and multiple
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define void @update(<5 x i16>* %dst, <5 x i16>* %src, i32 %n) nounwind {
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entry:
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%dst.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
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%src.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
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%n.addr = alloca i32 ; <i32*> [#uses=2]
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%v = alloca <5 x i16>, align 16 ; <<5 x i16>*> [#uses=1]
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%i = alloca i32, align 4 ; <i32*> [#uses=6]
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store <5 x i16>* %dst, <5 x i16>** %dst.addr
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store <5 x i16>* %src, <5 x i16>** %src.addr
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store i32 %n, i32* %n.addr
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store <5 x i16> < i16 1, i16 1, i16 1, i16 0, i16 0 >, <5 x i16>* %v
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store i32 0, i32* %i
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br label %forcond
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forcond: ; preds = %forinc, %entry
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%tmp = load i32, i32* %i ; <i32> [#uses=1]
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%tmp1 = load i32, i32* %n.addr ; <i32> [#uses=1]
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%cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
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br i1 %cmp, label %forbody, label %afterfor
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forbody: ; preds = %forcond
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%tmp2 = load i32, i32* %i ; <i32> [#uses=1]
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%tmp3 = load <5 x i16>*, <5 x i16>** %dst.addr ; <<5 x i16>*> [#uses=1]
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%arrayidx = getelementptr <5 x i16>, <5 x i16>* %tmp3, i32 %tmp2 ; <<5 x i16>*> [#uses=1]
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%tmp4 = load i32, i32* %i ; <i32> [#uses=1]
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%tmp5 = load <5 x i16>*, <5 x i16>** %src.addr ; <<5 x i16>*> [#uses=1]
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%arrayidx6 = getelementptr <5 x i16>, <5 x i16>* %tmp5, i32 %tmp4 ; <<5 x i16>*> [#uses=1]
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%tmp7 = load <5 x i16>, <5 x i16>* %arrayidx6 ; <<5 x i16>> [#uses=1]
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%sub = sub <5 x i16> %tmp7, < i16 271, i16 271, i16 271, i16 271, i16 271 > ; <<5 x i16>> [#uses=1]
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%mul = mul <5 x i16> %sub, < i16 2, i16 4, i16 2, i16 2, i16 2 > ; <<5 x i16>> [#uses=1]
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store <5 x i16> %mul, <5 x i16>* %arrayidx
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br label %forinc
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forinc: ; preds = %forbody
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%tmp8 = load i32, i32* %i ; <i32> [#uses=1]
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%inc = add i32 %tmp8, 1 ; <i32> [#uses=1]
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store i32 %inc, i32* %i
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br label %forcond
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afterfor: ; preds = %forcond
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ret void
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}
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