forked from OSchip/llvm-project
339 lines
12 KiB
C++
339 lines
12 KiB
C++
//===--- AMDGPU.cpp - Implement AMDGPU target feature support -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements AMDGPU TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "clang/Basic/Builtins.h"
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#include "clang/Basic/LangOptions.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "clang/Frontend/CodeGenOptions.h"
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#include "llvm/ADT/StringSwitch.h"
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using namespace clang;
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using namespace clang::targets;
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namespace clang {
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namespace targets {
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// If you edit the description strings, make sure you update
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// getPointerWidthV().
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static const char *const DataLayoutStringR600 =
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"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
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static const char *const DataLayoutStringSIPrivateIsZero =
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"e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
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"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
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static const char *const DataLayoutStringSIGenericIsZero =
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"e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
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"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
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static const LangASMap AMDGPUPrivIsZeroDefIsGenMap = {
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4, // Default
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1, // opencl_global
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3, // opencl_local
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2, // opencl_constant
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0, // opencl_private
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4, // opencl_generic
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1, // cuda_device
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2, // cuda_constant
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3 // cuda_shared
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};
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static const LangASMap AMDGPUGenIsZeroDefIsGenMap = {
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0, // Default
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1, // opencl_global
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3, // opencl_local
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2, // opencl_constant
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5, // opencl_private
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0, // opencl_generic
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1, // cuda_device
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2, // cuda_constant
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3 // cuda_shared
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};
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static const LangASMap AMDGPUPrivIsZeroDefIsPrivMap = {
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0, // Default
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1, // opencl_global
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3, // opencl_local
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2, // opencl_constant
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0, // opencl_private
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4, // opencl_generic
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1, // cuda_device
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2, // cuda_constant
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3 // cuda_shared
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};
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static const LangASMap AMDGPUGenIsZeroDefIsPrivMap = {
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5, // Default
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1, // opencl_global
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3, // opencl_local
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2, // opencl_constant
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5, // opencl_private
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0, // opencl_generic
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1, // cuda_device
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2, // cuda_constant
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3 // cuda_shared
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};
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} // namespace targets
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} // namespace clang
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const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
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#include "clang/Basic/BuiltinsAMDGPU.def"
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};
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const char *const AMDGPUTargetInfo::GCCRegNames[] = {
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"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
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"v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
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"v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
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"v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
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"v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
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"v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
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"v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
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"v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
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"v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
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"v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
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"v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
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"v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
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"v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
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"v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
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"v126", "v127", "v128", "v129", "v130", "v131", "v132", "v133", "v134",
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"v135", "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
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"v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", "v152",
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"v153", "v154", "v155", "v156", "v157", "v158", "v159", "v160", "v161",
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"v162", "v163", "v164", "v165", "v166", "v167", "v168", "v169", "v170",
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"v171", "v172", "v173", "v174", "v175", "v176", "v177", "v178", "v179",
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"v180", "v181", "v182", "v183", "v184", "v185", "v186", "v187", "v188",
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"v189", "v190", "v191", "v192", "v193", "v194", "v195", "v196", "v197",
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"v198", "v199", "v200", "v201", "v202", "v203", "v204", "v205", "v206",
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"v207", "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
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"v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", "v224",
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"v225", "v226", "v227", "v228", "v229", "v230", "v231", "v232", "v233",
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"v234", "v235", "v236", "v237", "v238", "v239", "v240", "v241", "v242",
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"v243", "v244", "v245", "v246", "v247", "v248", "v249", "v250", "v251",
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"v252", "v253", "v254", "v255", "s0", "s1", "s2", "s3", "s4",
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"s5", "s6", "s7", "s8", "s9", "s10", "s11", "s12", "s13",
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"s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
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"s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
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"s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40",
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"s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49",
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"s50", "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58",
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"s59", "s60", "s61", "s62", "s63", "s64", "s65", "s66", "s67",
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"s68", "s69", "s70", "s71", "s72", "s73", "s74", "s75", "s76",
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"s77", "s78", "s79", "s80", "s81", "s82", "s83", "s84", "s85",
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"s86", "s87", "s88", "s89", "s90", "s91", "s92", "s93", "s94",
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"s95", "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
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"s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", "s112",
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"s113", "s114", "s115", "s116", "s117", "s118", "s119", "s120", "s121",
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"s122", "s123", "s124", "s125", "s126", "s127", "exec", "vcc", "scc",
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"m0", "flat_scratch", "exec_lo", "exec_hi", "vcc_lo", "vcc_hi",
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"flat_scratch_lo", "flat_scratch_hi"
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};
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ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
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return llvm::makeArrayRef(GCCRegNames);
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}
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bool AMDGPUTargetInfo::initFeatureMap(
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llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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const std::vector<std::string> &FeatureVec) const {
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// XXX - What does the member GPU mean if device name string passed here?
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if (getTriple().getArch() == llvm::Triple::amdgcn) {
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if (CPU.empty())
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CPU = "tahiti";
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switch (parseAMDGCNName(CPU)) {
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case GK_GFX6:
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case GK_GFX7:
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break;
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case GK_GFX9:
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Features["gfx9-insts"] = true;
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LLVM_FALLTHROUGH;
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case GK_GFX8:
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Features["s-memrealtime"] = true;
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Features["16-bit-insts"] = true;
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Features["dpp"] = true;
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break;
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case GK_NONE:
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return false;
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default:
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llvm_unreachable("unhandled subtarget");
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}
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} else {
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if (CPU.empty())
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CPU = "r600";
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switch (parseR600Name(CPU)) {
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case GK_R600:
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case GK_R700:
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case GK_EVERGREEN:
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case GK_NORTHERN_ISLANDS:
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break;
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case GK_R600_DOUBLE_OPS:
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case GK_R700_DOUBLE_OPS:
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case GK_EVERGREEN_DOUBLE_OPS:
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case GK_CAYMAN:
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// TODO: Add fp64 when implemented.
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break;
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case GK_NONE:
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return false;
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default:
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llvm_unreachable("unhandled subtarget");
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}
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}
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return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec);
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}
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void AMDGPUTargetInfo::adjustTargetOptions(const CodeGenOptions &CGOpts,
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TargetOptions &TargetOpts) const {
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bool hasFP32Denormals = false;
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bool hasFP64Denormals = false;
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for (auto &I : TargetOpts.FeaturesAsWritten) {
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if (I == "+fp32-denormals" || I == "-fp32-denormals")
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hasFP32Denormals = true;
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if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals")
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hasFP64Denormals = true;
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}
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if (!hasFP32Denormals)
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TargetOpts.Features.push_back(
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(Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && !CGOpts.FlushDenorm
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? '+'
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: '-') +
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Twine("fp32-denormals"))
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.str());
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// Always do not flush fp64 or fp16 denorms.
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if (!hasFP64Denormals && hasFP64)
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TargetOpts.Features.push_back("+fp64-fp16-denormals");
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}
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constexpr AMDGPUTargetInfo::NameGPUKind AMDGPUTargetInfo::R600Names[];
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constexpr AMDGPUTargetInfo::NameGPUKind AMDGPUTargetInfo::AMDGCNNames[];
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AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseR600Name(StringRef Name) {
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const auto *Result = llvm::find_if(
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R600Names, [Name](const NameGPUKind &Kind) { return Kind.Name == Name; });
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if (Result == std::end(R600Names))
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return GK_NONE;
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return Result->Kind;
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}
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AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
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const auto *Result =
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llvm::find_if(AMDGCNNames, [Name](const NameGPUKind &Kind) {
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return Kind.Name == Name;
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});
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if (Result == std::end(AMDGCNNames))
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return GK_NONE;
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return Result->Kind;
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}
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void AMDGPUTargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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if (getTriple().getArch() == llvm::Triple::amdgcn)
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llvm::for_each(AMDGCNNames, [&Values](const NameGPUKind &Kind) {
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Values.emplace_back(Kind.Name);});
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else
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llvm::for_each(R600Names, [&Values](const NameGPUKind &Kind) {
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Values.emplace_back(Kind.Name);});
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}
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void AMDGPUTargetInfo::setAddressSpaceMap(bool DefaultIsPrivate) {
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if (isGenericZero(getTriple())) {
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AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap
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: &AMDGPUGenIsZeroDefIsGenMap;
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} else {
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AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap
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: &AMDGPUPrivIsZeroDefIsGenMap;
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}
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}
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AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple,
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const TargetOptions &Opts)
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: TargetInfo(Triple),
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GPU(isAMDGCN(Triple) ? GK_GFX6 : parseR600Name(Opts.CPU)),
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hasFP64(false), hasFMAF(false), hasLDEXPF(false),
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AS(isGenericZero(Triple)) {
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if (getTriple().getArch() == llvm::Triple::amdgcn) {
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hasFP64 = true;
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hasFMAF = true;
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hasLDEXPF = true;
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}
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if (getTriple().getArch() == llvm::Triple::r600) {
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if (GPU == GK_EVERGREEN_DOUBLE_OPS || GPU == GK_CAYMAN) {
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hasFMAF = true;
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}
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}
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auto IsGenericZero = isGenericZero(Triple);
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resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn
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? (IsGenericZero ? DataLayoutStringSIGenericIsZero
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: DataLayoutStringSIPrivateIsZero)
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: DataLayoutStringR600);
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assert(DataLayout->getAllocaAddrSpace() == AS.Private);
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setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D ||
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Triple.getEnvironment() == llvm::Triple::OpenCL ||
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Triple.getEnvironmentName() == "amdgizcl" ||
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!isAMDGCN(Triple));
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UseAddrSpaceMapMangling = true;
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// Set pointer width and alignment for target address space 0.
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PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits();
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if (getMaxPointerWidth() == 64) {
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LongWidth = LongAlign = 64;
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SizeType = UnsignedLong;
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PtrDiffType = SignedLong;
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IntPtrType = SignedLong;
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}
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
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}
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void AMDGPUTargetInfo::adjust(LangOptions &Opts) {
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TargetInfo::adjust(Opts);
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setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple()));
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}
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ArrayRef<Builtin::Info> AMDGPUTargetInfo::getTargetBuiltins() const {
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return llvm::makeArrayRef(BuiltinInfo, clang::AMDGPU::LastTSBuiltin -
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Builtin::FirstTSBuiltin);
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}
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void AMDGPUTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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if (getTriple().getArch() == llvm::Triple::amdgcn)
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Builder.defineMacro("__AMDGCN__");
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else
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Builder.defineMacro("__R600__");
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if (hasFMAF)
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Builder.defineMacro("__HAS_FMAF__");
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if (hasLDEXPF)
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Builder.defineMacro("__HAS_LDEXPF__");
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if (hasFP64)
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Builder.defineMacro("__HAS_FP64__");
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}
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