forked from OSchip/llvm-project
822 lines
37 KiB
C++
822 lines
37 KiB
C++
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86ISELLOWERING_H
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#define X86ISELLOWERING_H
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#include "X86Subtarget.h"
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#include "X86RegisterInfo.h"
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#include "X86MachineFunctionInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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namespace llvm {
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namespace X86ISD {
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// X86 Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// BSF - Bit scan forward.
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/// BSR - Bit scan reverse.
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BSF,
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BSR,
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/// SHLD, SHRD - Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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SHRD,
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/// FAND - Bitwise logical AND of floating point values. This corresponds
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/// to X86::ANDPS or X86::ANDPD.
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FAND,
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/// FOR - Bitwise logical OR of floating point values. This corresponds
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/// to X86::ORPS or X86::ORPD.
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FOR,
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/// FXOR - Bitwise logical XOR of floating point values. This corresponds
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/// to X86::XORPS or X86::XORPD.
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FXOR,
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/// FSRL - Bitwise logical right shift of floating point values. These
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/// corresponds to X86::PSRLDQ.
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FSRL,
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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/// also produces a flag).
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FILD,
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FILD_FLAG,
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/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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/// has two inputs (token chain and address) and two outputs (int value
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/// and token chain).
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// CALL - These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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///
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/// #0 - The incoming token chain
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/// #1 - The callee
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/// #2 - The number of arg bytes the caller pushes on the stack.
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/// #3 - The number of arg bytes the callee pops off the stack.
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/// #4 - The value to pass in AL/AX/EAX (optional)
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/// #5 - The value to pass in DL/DX/EDX (optional)
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///
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/// The result values of these nodes are:
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///
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/// #0 - The outgoing token chain
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/// #1 - The first register result value (optional)
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/// #2 - The second register result value (optional)
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///
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CALL,
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/// RDTSC_DAG - This operation implements the lowering for
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/// readcyclecounter
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RDTSC_DAG,
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/// X86 compare and logical compare instructions.
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CMP, COMI, UCOMI,
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/// X86 bit-test instructions.
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BT,
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/// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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// Same as SETCC except it's materialized with a sbb and the value is all
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// one's or all zero's.
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SETCC_CARRY,
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/// X86 conditional moves. Operand 0 and operand 1 are the two values
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/// to select from. Operand 2 is the condition code, and operand 3 is the
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/// flag operand produced by a CMP or TEST instruction. It also writes a
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/// flag result.
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CMOV,
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/// X86 conditional branches. Operand 0 is the chain operand, operand 1
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/// is the block to branch if condition is true, operand 2 is the
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/// condition code, and operand 3 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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/// Return with a flag operand. Operand 0 is the chain operand, operand
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/// 1 is the number of bytes of stack to pop.
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RET_FLAG,
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/// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
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REP_STOS,
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/// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
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REP_MOVS,
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/// GlobalBaseReg - On Darwin, this node represents the result of the popl
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// Wrapper - A wrapper node for TargetConstantPool,
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/// TargetExternalSymbol, and TargetGlobalAddress.
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Wrapper,
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/// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
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/// relative displacements.
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WrapperRIP,
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/// MOVQ2DQ - Copies a 64-bit value from a vector to another vector.
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/// Can be used to move a vector value from a MMX register to a XMM
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/// register.
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MOVQ2DQ,
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/// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRB.
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PEXTRB,
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/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRW.
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PEXTRW,
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/// INSERTPS - Insert any element of a 4 x float vector into any element
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/// of a destination 4 x floatvector.
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INSERTPS,
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/// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRB.
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PINSRB,
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/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRW.
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PINSRW, MMX_PINSRW,
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/// PSHUFB - Shuffle 16 8-bit values within a vector.
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PSHUFB,
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/// FMAX, FMIN - Floating point max and min.
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///
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FMAX, FMIN,
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/// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
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/// approximation. Note that these typically require refinement
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/// in order to obtain suitable precision.
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FRSQRT, FRCP,
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// TLSADDR - Thread Local Storage.
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TLSADDR,
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// SegmentBaseAddress - The address segment:0
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SegmentBaseAddress,
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// EH_RETURN - Exception Handling helpers.
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EH_RETURN,
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/// TC_RETURN - Tail call return.
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/// operand #0 chain
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/// operand #1 callee (register or absolute)
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/// operand #2 stack adjustment
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/// operand #3 optional in flag
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TC_RETURN,
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// LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
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LCMPXCHG_DAG,
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LCMPXCHG8_DAG,
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// FNSTCW16m - Store FP control world into i16 memory.
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FNSTCW16m,
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// VZEXT_MOVL - Vector move low and zero extend.
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VZEXT_MOVL,
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// VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
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VZEXT_LOAD,
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// VSHL, VSRL - Vector logical left / right shift.
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VSHL, VSRL,
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// CMPPD, CMPPS - Vector double/float comparison.
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// CMPPD, CMPPS - Vector double/float comparison.
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CMPPD, CMPPS,
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// PCMP* - Vector integer comparisons.
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PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
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PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
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// ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
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ADD, SUB, SMUL, UMUL,
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INC, DEC, OR, XOR, AND,
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// MUL_IMM - X86 specific multiply by immediate.
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MUL_IMM,
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// PTEST - Vector bitwise comparisons
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PTEST,
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// VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
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// according to %al. An operator is needed so that this can be expanded
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// with control flow.
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VASTART_SAVE_XMM_REGS,
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// MINGW_ALLOCA - MingW's __alloca call to do stack probing.
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MINGW_ALLOCA,
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// ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
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// ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
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// Atomic 64-bit binary operations.
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ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
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ATOMSUB64_DAG,
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ATOMOR64_DAG,
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ATOMXOR64_DAG,
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ATOMAND64_DAG,
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ATOMNAND64_DAG,
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ATOMSWAP64_DAG
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// WARNING: Do not add anything in the end unless you want the node to
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// have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
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// thought as target memory ops!
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};
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}
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/// Define some predicates that are used for node matching.
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namespace X86 {
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFDMask(ShuffleVectorSDNode *N);
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/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFHWMask(ShuffleVectorSDNode *N);
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/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFLWMask(ShuffleVectorSDNode *N);
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to SHUFP*.
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bool isSHUFPMask(ShuffleVectorSDNode *N);
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/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
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bool isMOVHLPSMask(ShuffleVectorSDNode *N);
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/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
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/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
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/// <2, 3, 2, 3>
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bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
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/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
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bool isMOVLPMask(ShuffleVectorSDNode *N);
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/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
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/// as well as MOVLHPS.
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bool isMOVLHPSMask(ShuffleVectorSDNode *N);
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/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKL.
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bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
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/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKH.
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bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
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/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
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/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
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/// <0, 0, 1, 1>
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bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
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/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
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/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
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/// <2, 2, 3, 3>
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bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
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/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSS,
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/// MOVSD, and MOVD, i.e. setting the lowest element.
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bool isMOVLMask(ShuffleVectorSDNode *N);
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
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bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
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/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
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bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
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/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVDDUP.
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bool isMOVDDUPMask(ShuffleVectorSDNode *N);
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/// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PALIGNR.
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bool isPALIGNRMask(ShuffleVectorSDNode *N);
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/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
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/// instructions.
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unsigned getShuffleSHUFImmediate(SDNode *N);
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/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
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unsigned getShufflePSHUFHWImmediate(SDNode *N);
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/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
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unsigned getShufflePSHUFLWImmediate(SDNode *N);
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/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
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/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
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unsigned getShufflePALIGNRImmediate(SDNode *N);
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/// isZeroNode - Returns true if Elt is a constant zero or a floating point
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/// constant +0.0.
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bool isZeroNode(SDValue Elt);
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/// isOffsetSuitableForCodeModel - Returns true of the given offset can be
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/// fit into displacement field of the instruction.
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bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
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bool hasSymbolicDisplacement = true);
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}
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//===--------------------------------------------------------------------===//
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// X86TargetLowering - X86 Implementation of the TargetLowering interface
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class X86TargetLowering : public TargetLowering {
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public:
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explicit X86TargetLowering(X86TargetMachine &TM);
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/// getPICBaseSymbol - Return the X86-32 PIC base.
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MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const;
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virtual unsigned getJumpTableEncoding() const;
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virtual const MCExpr *
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LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
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const MachineBasicBlock *MBB, unsigned uid,
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MCContext &Ctx) const;
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/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
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/// jumptable.
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virtual SDValue getPICJumpTableRelocBase(SDValue Table,
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SelectionDAG &DAG) const;
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virtual const MCExpr *
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getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
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unsigned JTI, MCContext &Ctx) const;
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/// getStackPtrReg - Return the stack pointer register we are using: either
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/// ESP or RSP.
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unsigned getStackPtrReg() const { return X86StackPtr; }
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/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
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/// function arguments in the caller parameter area. For X86, aggregates
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/// that contains are placed at 16-byte boundaries while the rest are at
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/// 4-byte boundaries.
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virtual unsigned getByValTypeAlignment(const Type *Ty) const;
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/// getOptimalMemOpType - Returns the target specific optimal type for load
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/// and store operations as a result of memset, memcpy, and memmove
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/// lowering. If DstAlign is zero that means it's safe to destination
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/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
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/// means there isn't a need to check it against alignment requirement,
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/// probably because the source does not need to be loaded. If
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/// 'NonScalarIntSafe' is true, that means it's safe to return a
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/// non-scalar-integer type, e.g. empty string source, constant, or loaded
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/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
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/// constant so it does not need to be loaded.
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/// It returns EVT::Other if the type should be determined using generic
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/// target-independent logic.
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virtual EVT
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getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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bool NonScalarIntSafe, bool MemcpyStrSrc,
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MachineFunction &MF) const;
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/// allowsUnalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses. of the specified type.
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virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
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return true;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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/// isTypeDesirableForOp - Return true if the target has native support for
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/// the specified value type and it is 'desirable' to use the type for the
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/// given node type. e.g. On x86 i16 is legal, but undesirable since i16
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/// instruction encodings are longer and some i16 instructions are slow.
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virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
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/// isTypeDesirable - Return true if the target has native support for the
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/// specified value type and it is 'desirable' to use the type. e.g. On x86
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/// i16 is legal, but undesirable since i16 instruction encodings are longer
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/// and some i16 instructions are slow.
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virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
|
|
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
|
|
|
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
|
virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
|
|
|
|
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
|
|
/// in Mask are known to be either zero or one and return them in the
|
|
/// KnownZero/KnownOne bitsets.
|
|
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
|
|
const APInt &Mask,
|
|
APInt &KnownZero,
|
|
APInt &KnownOne,
|
|
const SelectionDAG &DAG,
|
|
unsigned Depth = 0) const;
|
|
|
|
virtual bool
|
|
isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
|
|
|
|
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
|
|
|
|
virtual bool ExpandInlineAsm(CallInst *CI) const;
|
|
|
|
ConstraintType getConstraintType(const std::string &Constraint) const;
|
|
|
|
std::vector<unsigned>
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
EVT VT) const;
|
|
|
|
virtual const char *LowerXConstraint(EVT ConstraintVT) const;
|
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
|
|
/// true it means one of the asm constraint of the inline asm instruction
|
|
/// being processed is 'm'.
|
|
virtual void LowerAsmOperandForConstraint(SDValue Op,
|
|
char ConstraintLetter,
|
|
bool hasMemory,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const;
|
|
|
|
/// getRegForInlineAsmConstraint - Given a physical register constraint
|
|
/// (e.g. {edx}), return the register number and the register class for the
|
|
/// register. This should only be used for C_Register constraints. On
|
|
/// error, this returns a register number of 0.
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
|
EVT VT) const;
|
|
|
|
/// isLegalAddressingMode - Return true if the addressing mode represented
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
|
virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
|
|
|
|
/// isTruncateFree - Return true if it's free to truncate a value of
|
|
/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
|
|
/// register EAX to i16 by referencing its sub-register AX.
|
|
virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
|
|
virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
|
|
|
|
/// isZExtFree - Return true if any actual instruction that defines a
|
|
/// value of type Ty1 implicit zero-extends the value to Ty2 in the result
|
|
/// register. This does not necessarily include registers defined in
|
|
/// unknown ways, such as incoming arguments, or copies from unknown
|
|
/// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
|
|
/// does not necessarily apply to truncate instructions. e.g. on x86-64,
|
|
/// all instructions that define 32-bit values implicit zero-extend the
|
|
/// result out to 64 bits.
|
|
virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
|
|
virtual bool isZExtFree(EVT VT1, EVT VT2) const;
|
|
|
|
/// isNarrowingProfitable - Return true if it's profitable to narrow
|
|
/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
|
|
/// from i32 to i8 but not from i32 to i16.
|
|
virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
|
|
|
|
/// isFPImmLegal - Returns true if the target can instruction select the
|
|
/// specified FP immediate natively. If false, the legalizer will
|
|
/// materialize the FP immediate as a load from a constant pool.
|
|
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
|
|
|
/// isShuffleMaskLegal - Targets can use this to indicate that they only
|
|
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
|
|
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
|
|
/// values are assumed to be legal.
|
|
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
EVT VT) const;
|
|
|
|
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
|
|
/// used by Targets can use this to indicate if there is a suitable
|
|
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
|
|
/// pool entry.
|
|
virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
EVT VT) const;
|
|
|
|
/// ShouldShrinkFPConstant - If true, then instruction selection should
|
|
/// seek to shrink the FP constant of the specified type to a smaller type
|
|
/// in order to save space and / or reduce runtime.
|
|
virtual bool ShouldShrinkFPConstant(EVT VT) const {
|
|
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
|
|
// expensive than a straight movsd. On the other hand, it's important to
|
|
// shrink long double fp constant since fldt is very slow.
|
|
return !X86ScalarSSEf64 || VT == MVT::f80;
|
|
}
|
|
|
|
const X86Subtarget* getSubtarget() const {
|
|
return Subtarget;
|
|
}
|
|
|
|
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
|
|
/// computed in an SSE register, not on the X87 floating point stack.
|
|
bool isScalarFPTypeInSSEReg(EVT VT) const {
|
|
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
|
|
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
|
|
}
|
|
|
|
/// createFastISel - This method returns a target specific FastISel object,
|
|
/// or null if the target does not support "fast" ISel.
|
|
virtual FastISel *
|
|
createFastISel(MachineFunction &mf,
|
|
DenseMap<const Value *, unsigned> &,
|
|
DenseMap<const BasicBlock *, MachineBasicBlock *> &,
|
|
DenseMap<const AllocaInst *, int> &,
|
|
std::vector<std::pair<MachineInstr*, unsigned> > &
|
|
#ifndef NDEBUG
|
|
, SmallSet<const Instruction *, 8> &
|
|
#endif
|
|
) const;
|
|
|
|
/// getFunctionAlignment - Return the Log2 alignment of this function.
|
|
virtual unsigned getFunctionAlignment(const Function *F) const;
|
|
|
|
private:
|
|
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
|
|
/// make the right decision when generating code for different targets.
|
|
const X86Subtarget *Subtarget;
|
|
const X86RegisterInfo *RegInfo;
|
|
const TargetData *TD;
|
|
|
|
/// X86StackPtr - X86 physical register used as stack ptr.
|
|
unsigned X86StackPtr;
|
|
|
|
/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
|
|
/// floating point ops.
|
|
/// When SSE is available, use it for f32 operations.
|
|
/// When SSE2 is available, use it for f64 operations.
|
|
bool X86ScalarSSEf32;
|
|
bool X86ScalarSSEf64;
|
|
|
|
/// LegalFPImmediates - A list of legal fp immediates.
|
|
std::vector<APFloat> LegalFPImmediates;
|
|
|
|
/// addLegalFPImmediate - Indicate that this x86 target can instruction
|
|
/// select the specified FP immediate natively.
|
|
void addLegalFPImmediate(const APFloat& Imm) {
|
|
LegalFPImmediates.push_back(Imm);
|
|
}
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue LowerMemArgument(SDValue Chain,
|
|
CallingConv::ID CallConv,
|
|
const SmallVectorImpl<ISD::InputArg> &ArgInfo,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA, MachineFrameInfo *MFI,
|
|
unsigned i) const;
|
|
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA,
|
|
ISD::ArgFlagsTy Flags) const;
|
|
|
|
// Call lowering helpers.
|
|
|
|
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
|
|
/// for tail call optimization. Targets which want to do tail call
|
|
/// optimization should implement this function.
|
|
bool IsEligibleForTailCallOptimization(SDValue Callee,
|
|
CallingConv::ID CalleeCC,
|
|
bool isVarArg,
|
|
bool isCalleeStructRet,
|
|
bool isCallerStructRet,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SelectionDAG& DAG) const;
|
|
bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
|
|
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
|
|
SDValue Chain, bool IsTailCall, bool Is64Bit,
|
|
int FPDiff, DebugLoc dl) const;
|
|
|
|
CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
|
|
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
|
|
SelectionDAG &DAG) const;
|
|
|
|
std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
|
|
bool isSigned) const;
|
|
|
|
SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
|
|
SelectionDAG &DAG) const;
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
|
|
int64_t Offset, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
|
|
SelectionDAG &DAG) const;
|
|
SDValue LowerBIT_CONVERT(SDValue op, SelectionDAG &DAG) const;
|
|
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerToBT(SDValue And, ISD::CondCode CC,
|
|
DebugLoc dl, SelectionDAG &DAG) const;
|
|
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
virtual SDValue
|
|
LowerFormalArguments(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
virtual SDValue
|
|
LowerCall(SDValue Chain, SDValue Callee,
|
|
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
virtual SDValue
|
|
LowerReturn(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
DebugLoc dl, SelectionDAG &DAG) const;
|
|
|
|
virtual bool
|
|
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<EVT> &OutTys,
|
|
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
|
|
SelectionDAG &DAG) const;
|
|
|
|
void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
|
|
SelectionDAG &DAG, unsigned NewOp) const;
|
|
|
|
/// Utility function to emit string processing sse4.2 instructions
|
|
/// that return in xmm0.
|
|
/// This takes the instruction to expand, the associated machine basic
|
|
/// block, the number of args, and whether or not the second arg is
|
|
/// in memory or not.
|
|
MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
|
|
unsigned argNum, bool inMem) const;
|
|
|
|
/// Utility function to emit atomic bitwise operations (and, or, xor).
|
|
/// It takes the bitwise instruction to expand, the associated machine basic
|
|
/// block, and the associated X86 opcodes for reg/reg and reg/imm.
|
|
MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
|
|
MachineInstr *BInstr,
|
|
MachineBasicBlock *BB,
|
|
unsigned regOpc,
|
|
unsigned immOpc,
|
|
unsigned loadOpc,
|
|
unsigned cxchgOpc,
|
|
unsigned copyOpc,
|
|
unsigned notOpc,
|
|
unsigned EAXreg,
|
|
TargetRegisterClass *RC,
|
|
bool invSrc = false) const;
|
|
|
|
MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
|
|
MachineInstr *BInstr,
|
|
MachineBasicBlock *BB,
|
|
unsigned regOpcL,
|
|
unsigned regOpcH,
|
|
unsigned immOpcL,
|
|
unsigned immOpcH,
|
|
bool invSrc = false) const;
|
|
|
|
/// Utility function to emit atomic min and max. It takes the min/max
|
|
/// instruction to expand, the associated basic block, and the associated
|
|
/// cmov opcode for moving the min or max value.
|
|
MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
|
|
MachineBasicBlock *BB,
|
|
unsigned cmovOpc) const;
|
|
|
|
/// Utility function to emit the xmm reg save portion of va_start.
|
|
MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
|
|
MachineInstr *BInstr,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredMingwAlloca(MachineInstr *MI,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
/// Emit nodes that will be selected as "test Op0,Op0", or something
|
|
/// equivalent, for use with the given x86 condition code.
|
|
SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
|
|
|
|
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
|
|
/// equivalent, for use with the given x86 condition code.
|
|
SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
|
|
SelectionDAG &DAG) const;
|
|
};
|
|
|
|
namespace X86 {
|
|
FastISel *createFastISel(MachineFunction &mf,
|
|
DenseMap<const Value *, unsigned> &,
|
|
DenseMap<const BasicBlock *, MachineBasicBlock *> &,
|
|
DenseMap<const AllocaInst *, int> &,
|
|
std::vector<std::pair<MachineInstr*, unsigned> > &
|
|
#ifndef NDEBUG
|
|
, SmallSet<const Instruction*, 8> &
|
|
#endif
|
|
);
|
|
}
|
|
}
|
|
|
|
#endif // X86ISELLOWERING_H
|