forked from OSchip/llvm-project
50 lines
1.3 KiB
LLVM
50 lines
1.3 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
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target triple = "thumbv7-apple-ios"
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; CHECK: local_split
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;
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; The load must go into d0-15 which are all clobbered by the asm.
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; RAGreedy should split the range and use d16-d31 to avoid a spill.
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;
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; CHECK: vldr s
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; CHECK-NOT: vstr
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; CHECK: vadd.f32
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; CHECK-NOT: vstr
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; CHECK: vorr
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; CHECK: vstr s
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define void @local_split(float* nocapture %p) nounwind ssp {
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entry:
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%x = load float, float* %p, align 4
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%a = fadd float %x, 1.0
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tail call void asm sideeffect "", "~{d0},~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind
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store float %a, float* %p, align 4
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ret void
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}
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; CHECK: global_split
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;
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; Same thing, but across basic blocks.
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;
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; CHECK: vldr s
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; CHECK-NOT: vstr
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; CHECK: vadd.f32
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; CHECK-NOT: vstr
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; CHECK: vorr
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; CHECK: vstr s
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define void @global_split(float* nocapture %p1, float* nocapture %p2) nounwind ssp {
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entry:
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%0 = load float, float* %p1, align 4
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%add = fadd float %0, 1.000000e+00
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tail call void asm sideeffect "", "~{d0},~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind
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%cmp = fcmp ogt float %add, 0.000000e+00
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store float %add, float* %p2, align 4
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br label %if.end
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if.end:
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store float %add, float* %p1, align 4
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ret void
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}
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