llvm-project/llvm/lib/MCA
Andrea Di Biagio 9853d0db1e [MCA][NFCI] Minor changes to InstrBuilder and Instruction.
This is based on the assumption that most simulated instructions don't define
more than one or two registers. This is true for example on x86, where
most instruction definitions don't declare more than one register write.

The default code region size has been increased from 8 to 16. This is based on
the assumption that, for small microbenchmarks, the typical code snippet size is
often less than 16 instructions.

mca::Instruction now uses bitfields to pack flags.
No functional change intended.
2021-05-31 17:05:13 +01:00
..
HardwareUnits [MCA] Refactor the InOrderIssueStage stage. NFCI 2021-05-27 22:28:04 +01:00
Stages [MCA] Minor changes to the InOrderIssueStage. NFC 2021-05-28 00:33:59 +01:00
CMakeLists.txt [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
CodeEmitter.cpp [MCA][NFCI] Minor changes to InstrBuilder and Instruction. 2021-05-31 17:05:13 +01:00
Context.cpp [MCA][NFCI] Minor changes to InstrBuilder and Instruction. 2021-05-31 17:05:13 +01:00
HWEventListener.cpp
InstrBuilder.cpp [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
Instruction.cpp [MCA] Improved handling of negative read-advance cycles. 2021-03-23 14:47:23 +00:00
Pipeline.cpp Revert "Remove redundant "std::move"s in return statements" 2020-02-10 07:07:40 -08:00
Support.cpp