forked from OSchip/llvm-project
99 lines
4.0 KiB
C++
99 lines
4.0 KiB
C++
//=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This class implements a deterministic finite automaton (DFA) based
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// packetizing mechanism for VLIW architectures. It provides APIs to
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// determine whether there exists a legal mapping of instructions to
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// functional unit assignments in a packet. The DFA is auto-generated from
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// the target's Schedule.td file.
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//
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// A DFA consists of 3 major elements: states, inputs, and transitions. For
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// the packetizing mechanism, the input is the set of instruction classes for
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// a target. The state models all possible combinations of functional unit
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// consumption for a given set of instructions in a packet. A transition
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// models the addition of an instruction to a packet. In the DFA constructed
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// by this class, if an instruction can be added to a packet, then a valid
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// transition exists from the corresponding state. Invalid transitions
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// indicate that the instruction cannot be added to the current packet.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCInstrItineraries.h"
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using namespace llvm;
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DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
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const unsigned *SET):
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InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
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DFAStateEntryTable(SET) {}
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//
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// ReadTable - Read the DFA transition table and update CachedTable.
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//
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// Format of the transition tables:
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// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
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// transitions
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// DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable
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// for the ith state
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//
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void DFAPacketizer::ReadTable(unsigned int state) {
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unsigned ThisState = DFAStateEntryTable[state];
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unsigned NextStateInTable = DFAStateEntryTable[state+1];
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// Early exit in case CachedTable has already contains this
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// state's transitions.
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if (CachedTable.count(UnsignPair(state,
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DFAStateInputTable[ThisState][0])))
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return;
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for (unsigned i = ThisState; i < NextStateInTable; i++)
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CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
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DFAStateInputTable[i][1];
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}
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state.
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bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
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unsigned FuncUnits = IS->getUnits();
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UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
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ReadTable(CurrentState);
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return (CachedTable.count(StateTrans) != 0);
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}
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change.
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void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
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unsigned FuncUnits = IS->getUnits();
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UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
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ReadTable(CurrentState);
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assert(CachedTable.count(StateTrans) != 0);
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CurrentState = CachedTable[StateTrans];
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}
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// canReserveResources - Check if the resources occupied by a machine
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// instruction are available in the current state.
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bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) {
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const llvm::MCInstrDesc &MID = MI->getDesc();
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return canReserveResources(&MID);
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}
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// reserveResources - Reserve the resources occupied by a machine
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// instruction and change the current state to reflect that change.
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void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
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const llvm::MCInstrDesc &MID = MI->getDesc();
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reserveResources(&MID);
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}
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