llvm-project/llvm/lib/CodeGen
Jeremy Morse f5e1b718a6 [DebugInfo] MachineSink: find more DBG_VALUEs to sink
In the Pre-RA machine sinker, previously we were relying on all DBG_VALUEs
being immediately after the instruction that defined their operands. This
isn't a valid assumption, as a variable location change doesn't
necessarily correspond to where the value is computed. In this patch, we
collect DBG_VALUEs that might need sinking as we walk through a block,
and sink all of them if their defining instruction is sunk.

This patch adds some copy propagation too, so that if we sink a copy inst,
the now non-dominated paths can use the copy source for the variable
location.

Differential Revision: https://reviews.llvm.org/D58386
2019-10-28 14:32:50 +00:00
..
AsmPrinter Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs." 2019-10-25 12:41:34 -07:00
GlobalISel GlobalISel: Implement widenScalar for G_INSERT_VECTOR_ELT 2019-10-25 13:55:07 -07:00
MIRParser [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
SelectionDAG [DAGCombiner] widen any_ext of popcount based on target support 2019-10-28 10:07:12 -04:00
AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker - silence static analyzer null dereference warning. NFCI. 2019-09-24 13:57:51 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp [SVE][IR] Scalable Vector size queries and IR instruction support 2019-10-08 12:53:54 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp [Alignment][NFC] Remove StoreInst::setAlignment(unsigned) 2019-10-03 13:17:21 +00:00
BasicTargetTransformInfo.cpp
BranchFolding.cpp [DebugInfo][If-Converter] Update call site info during the optimization 2019-10-08 15:43:12 +00:00
BranchFolding.h
BranchRelaxation.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
BreakFalseDeps.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
BuiltinGCs.cpp
CFIInstrInserter.cpp
CMakeLists.txt Reverted r375254 as it has broken some build bots for a long time. 2019-10-20 20:39:33 +00:00
CalcSpillWeights.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
CallingConvLower.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
CodeGen.cpp [NewPM] Port MachineModuleInfo to the new pass manager. 2019-09-30 17:54:50 +00:00
CodeGenPrepare.cpp [Alignment][NFC] Remove dependency on GlobalObject::setAlignment(unsigned) 2019-10-15 11:24:36 +00:00
CriticalAntiDepBreaker.cpp CriticalAntiDepBreaker - Assert that we've found the bottom of the critical path. NFCI. 2019-09-23 10:42:47 +00:00
CriticalAntiDepBreaker.h
DFAPacketizer.cpp Prune Analysis includes from SelectionDAG.h 2019-10-19 01:07:48 +00:00
DeadMachineInstructionElim.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
DetectDeadLanes.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
DwarfEHPrepare.cpp Add an optional list of blocks to avoid when looking for a path in isPotentiallyReachable. 2019-04-02 01:05:48 +00:00
EarlyIfConversion.cpp [CodeGen] Add a pass to do block predication on SSA machine IR. 2019-08-20 15:54:59 +00:00
EdgeBundles.cpp Fix parameter name comments using clang-tidy. NFC. 2019-07-16 04:46:31 +00:00
ExecutionDomainFix.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
ExpandMemCmp.cpp Revert "Reland "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."" 2019-09-10 10:39:09 +00:00
ExpandPostRAPseudos.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
ExpandReductions.cpp Change semantics of fadd/fmul vector reductions. 2019-06-11 08:22:10 +00:00
FEntryInserter.cpp
FaultMaps.cpp
FinalizeISel.cpp Rename ExpandISelPseudo->FinalizeISel, delay register reservation 2019-06-19 00:25:39 +00:00
FuncletLayout.cpp
GCMetadata.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
GCMetadataPrinter.cpp
GCRootLowering.cpp [NewPM] Port MachineModuleInfo to the new pass manager. 2019-09-30 17:54:50 +00:00
GCStrategy.cpp
GlobalMerge.cpp [Alignment][NFC] Remove dependency on GlobalObject::setAlignment(unsigned) 2019-10-15 11:24:36 +00:00
HardwareLoops.cpp Revert "[HardwareLoops] Optimisation remarks" 2019-10-16 10:55:06 +00:00
IfConversion.cpp [IfCvt][ARM] Optimise diamond if-conversion for code size 2019-10-10 09:58:28 +00:00
ImplicitNullChecks.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
IndirectBrExpandPass.cpp
InlineSpiller.cpp Move LiveRangeCalc header to publicily available position. NFC 2019-10-17 03:12:51 +00:00
InterferenceCache.cpp
InterferenceCache.h
InterleavedAccessPass.cpp
InterleavedLoadCombinePass.cpp InterleavedLoadCombine - merge isa<> and dyn_cast<> duplicates. NFCI. 2019-09-15 16:20:12 +00:00
IntrinsicLowering.cpp
LLVMBuild.txt
LLVMTargetMachine.cpp [Mips] Use appropriate private label prefix based on Mips ABI 2019-10-23 12:24:35 +02:00
LatencyPriorityQueue.cpp
LazyMachineBlockFrequencyInfo.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
LexicalScopes.cpp Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
LiveDebugValues.cpp Fix a variable typo in LiveDebugValues [NFC] 2019-10-25 11:21:43 +02:00
LiveDebugVariables.cpp [NFC] Replace a linked list in LiveDebugVariables pass with a DenseMap 2019-10-16 08:36:00 +00:00
LiveDebugVariables.h
LiveInterval.cpp LiveIntervals: Remove assertion 2019-09-12 23:46:51 +00:00
LiveIntervalUnion.cpp
LiveIntervals.cpp LiveIntervals: Fix handleMoveUp with subreg def moving across a def 2019-10-18 23:24:25 +00:00
LivePhysRegs.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
LiveRangeCalc.cpp Move LiveRangeCalc header to publicily available position. NFC 2019-10-17 03:12:51 +00:00
LiveRangeEdit.cpp [DebugInfo][If-Converter] Update call site info during the optimization 2019-10-08 15:43:12 +00:00
LiveRangeShrink.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
LiveRangeUtils.h
LiveRegMatrix.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
LiveRegUnits.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
LiveStacks.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
LiveVariables.cpp Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
LocalStackSlotAllocation.cpp [LLVM][Alignment] Introduce Alignment In MachineFrameInfo 2019-08-21 14:29:30 +00:00
LoopTraversal.cpp
LowLevelType.cpp
LowerEmuTLS.cpp [Alignment][NFC] Remove dependency on GlobalObject::setAlignment(unsigned) 2019-10-15 11:24:36 +00:00
MIRCanonicalizerPass.cpp Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
MIRNamerPass.cpp [MIR] MIRNamer pass for improving MIR test authoring experience. 2019-09-05 20:44:33 +00:00
MIRPrinter.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
MIRPrintingPass.cpp
MIRVRegNamerUtils.cpp Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
MIRVRegNamerUtils.h Hide implementation details in namespaces. 2019-09-17 12:56:29 +00:00
MachineBasicBlock.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
MachineBlockFrequencyInfo.cpp Reverted r375254 as it has broken some build bots for a long time. 2019-10-20 20:39:33 +00:00
MachineBlockPlacement.cpp Revert [CodeGen] Do the Simple Early Return in block-placement pass to optimize the blocks 2019-10-04 22:24:21 +00:00
MachineBranchProbabilityInfo.cpp
MachineCSE.cpp [DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locations 2019-09-02 12:28:36 +00:00
MachineCombiner.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
MachineCopyPropagation.cpp Revert "[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp" 2019-09-09 16:46:45 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp Reverted r375254 as it has broken some build bots for a long time. 2019-10-20 20:39:33 +00:00
MachineFrameInfo.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
MachineFunction.cpp Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs." 2019-10-25 12:41:34 -07:00
MachineFunctionPass.cpp [NewPM] Port MachineModuleInfo to the new pass manager. 2019-09-30 17:54:50 +00:00
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs." 2019-10-25 12:41:34 -07:00
MachineInstrBundle.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
MachineLICM.cpp [Dominators][CodeGen] Don't mark MachineDominatorTree as preserved in MachineLICM 2019-10-01 18:27:44 +00:00
MachineLoopInfo.cpp Reverted r375254 as it has broken some build bots for a long time. 2019-10-20 20:39:33 +00:00
MachineLoopUtils.cpp [ModuloSchedule] Peel out prologs and epilogs, generate actual code 2019-10-02 12:46:44 +00:00
MachineModuleInfo.cpp Second attempt to add iterator_range::empty() 2019-10-07 18:14:24 +00:00
MachineModuleInfoImpls.cpp
MachineOperand.cpp [Alignment][NFC] Finish transition for `Loads` 2019-10-21 15:10:26 +00:00
MachineOptimizationRemarkEmitter.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
MachineOutliner.cpp [DebugInfo][If-Converter] Update call site info during the optimization 2019-10-08 15:43:12 +00:00
MachinePipeliner.cpp [ModuloSchedule] Peel out prologs and epilogs, generate actual code 2019-10-02 12:46:44 +00:00
MachinePostDominators.cpp [Dominators][CodeGen] Add MachinePostDominatorTree verification 2019-10-01 15:23:27 +00:00
MachineRegionInfo.cpp
MachineRegisterInfo.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
MachineSSAUpdater.cpp MachineSSAUpdater: insert IMPLICIT_DEF at top of basic block 2019-10-08 12:46:20 +00:00
MachineScheduler.cpp [Dominators][CodeGen] Fix MachineDominatorTree preservation in PHIElimination 2019-10-01 18:27:17 +00:00
MachineSink.cpp [DebugInfo] MachineSink: find more DBG_VALUEs to sink 2019-10-28 14:32:50 +00:00
MachineTraceMetrics.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
MachineVerifier.cpp Move LiveRangeCalc header to publicily available position. NFC 2019-10-17 03:12:51 +00:00
MacroFusion.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
ModuloSchedule.cpp [ModuloSchedule] Do not remap terminators 2019-10-04 17:15:25 +00:00
OptimizePHIs.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
PHIElimination.cpp [Dominators][CodeGen] Fix MachineDominatorTree preservation in PHIElimination 2019-10-01 18:27:17 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
ParallelCG.cpp
PatchableFunction.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
PeepholeOptimizer.cpp [DebugInfo][If-Converter] Update call site info during the optimization 2019-10-08 15:43:12 +00:00
PostRAHazardRecognizer.cpp
PostRASchedulerList.cpp
PreISelIntrinsicLowering.cpp lowerObjCCall - silence static analyzer dyn_cast<CallInst> null dereference warnings. NFCI. 2019-09-24 10:46:30 +00:00
ProcessImplicitDefs.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
PrologEpilogInserter.cpp [LLVM][Alignment] Introduce Alignment In MachineFrameInfo 2019-08-21 14:29:30 +00:00
PseudoSourceValue.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
README.txt
ReachingDefAnalysis.cpp Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
RegAllocBase.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
RegAllocBase.h
RegAllocBasic.cpp
RegAllocFast.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
RegAllocGreedy.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
RegAllocPBQP.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
RegUsageInfoCollector.cpp Reverted r375425 as it broke some buildbots. 2019-10-21 19:11:40 +00:00
RegUsageInfoPropagate.cpp [IPRA] Don't rely on non-exact function definitions 2019-07-19 09:59:26 +00:00
RegisterClassInfo.cpp [ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsize 2019-07-03 09:58:52 +00:00
RegisterCoalescer.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
RegisterScavenging.cpp RegScavenger: Use Register 2019-08-23 18:25:34 +00:00
RegisterUsageInfo.cpp
RenameIndependentSubregs.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
ResetMachineFunctionPass.cpp
SafeStack.cpp Change TargetLibraryInfo analysis passes to always require Function 2019-09-07 03:09:36 +00:00
SafeStackColoring.cpp
SafeStackColoring.h
SafeStackLayout.cpp
SafeStackLayout.h
ScalarizeMaskedMemIntrin.cpp [NFC][TTI] Add Alignment for isLegalMasked[Load/Store] 2019-10-14 10:00:21 +00:00
ScheduleDAG.cpp [ScheduleDAGRRList] Recompute topological ordering on demand. 2019-04-17 15:05:29 +00:00
ScheduleDAGInstrs.cpp Prune Analysis includes from SelectionDAG.h 2019-10-19 01:07:48 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGCLowering.cpp
ShrinkWrap.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
SjLjEHPrepare.cpp [Alignment][NFC] Convert AllocaInst to MaybeAlign 2019-10-25 22:41:34 +02:00
SlotIndexes.cpp SlotIndexes: delete unused functions 2019-06-23 16:05:29 +00:00
SpillPlacement.cpp
SpillPlacement.h
Spiller.h
SplitKit.cpp Move LiveRangeCalc header to publicily available position. NFC 2019-10-17 03:12:51 +00:00
SplitKit.h Move LiveRangeCalc header to publicily available position. NFC 2019-10-17 03:12:51 +00:00
StackColoring.cpp Use llvm::stable_sort 2019-04-23 14:51:27 +00:00
StackMapLivenessAnalysis.cpp
StackMaps.cpp MCRegisterInfo: Merge getLLVMRegNum and getLLVMRegNumFromEH 2019-09-24 09:31:02 +00:00
StackProtector.cpp [SSP] [3/3] cmpxchg and addrspacecast instructions can now 2019-09-30 15:11:23 +00:00
StackSlotColoring.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
SwiftErrorValueTracking.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
SwitchLoweringUtils.cpp Revert r372893 "[CodeGen] Replace -max-jump-table-size with -max-jump-table-targets" 2019-09-27 09:54:26 +00:00
TailDuplication.cpp
TailDuplicator.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
TargetFrameLoweringImpl.cpp Reverted r375425 as it broke some buildbots. 2019-10-21 19:11:40 +00:00
TargetInstrInfo.cpp [DebugInfo] Stop describing imms in TargetInstrInfo's describeLoadedValue() impl 2019-10-23 11:41:29 +02:00
TargetLoweringBase.cpp [AArch64][SVE] Add SPLAT_VECTOR ISD Node 2019-10-18 11:48:35 +00:00
TargetLoweringObjectFileImpl.cpp Added support for "#pragma clang section relro=<name>" 2019-10-15 18:31:10 +00:00
TargetOptionsImpl.cpp
TargetPassConfig.cpp Reapply r374743 with a fix for the ocaml binding 2019-10-14 16:15:14 +00:00
TargetRegisterInfo.cpp [TargetRegisterInfo] Remove SVT argument from getCommonSubClass. 2019-09-13 05:24:37 +00:00
TargetSchedule.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
TargetSubtargetInfo.cpp
TwoAddressInstructionPass.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
UnreachableBlockElim.cpp [DebugInfo][If-Converter] Update call site info during the optimization 2019-10-08 15:43:12 +00:00
ValueTypes.cpp [MVT] Add v256i1 to MachineValueType 2019-09-20 15:19:20 +00:00
VirtRegMap.cpp Eliminate implicit Register->unsigned conversions in VirtRegMap. NFC 2019-08-13 00:55:24 +00:00
WasmEHPrepare.cpp
WinEHPrepare.cpp Fix parameter name comments using clang-tidy. NFC. 2019-07-16 04:46:31 +00:00
XRayInstrumentation.cpp [DebugInfo][If-Converter] Update call site info during the optimization 2019-10-08 15:43:12 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side
effects).  Once this is in place, it would be even better to have tblgen
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStacks analysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.