Simon Pilgrim 6b9bf7ecbc [X86][AVX] Prefer VPBLENDW+VPBLENDD to VPBLENDVB for v16i16 blend shuffles ... Noticed while looking at D49562 codegen - we can avoid a large constant mask load and a slow VPBLENDVB select op by using VPBLENDW+VPBLENDD instead. TODO: As discussed on the patch, we should investigate adding VPBLENDVB handling to target shuffle combining as well, that will allow us to extend this to VPBLENDW+VPBLENDW+VPBLENDD. Differential Revision: https://reviews.llvm.org/D50074 llvm-svn: 340913		2018-08-29 10:51:08 +00:00
..
AArch64	Start reserving x18 by default on Android targets.	2018-08-29 01:38:47 +00:00
AMDGPU	AMDGPU: Fix getInstSizeInBytes	2018-08-29 07:46:09 +00:00
ARC	…
ARM	[ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available.	2018-08-22 21:47:14 +00:00
AVR	…
BPF	bpf: add missing RegState to notify MachineInstr verifier necessary register usage	2018-07-27 16:58:52 +00:00
Generic	[DWARF] Unclamp line table version on Darwin for v5 and later.	2018-08-08 21:16:50 +00:00
Hexagon	[Pipeliner] Fix incorrect phi values in the epilog and kernel	2018-08-27 22:04:50 +00:00
Inputs	…
Lanai	…
MIR	Consistently use MemoryLocation::UnknownSize to indicate unknown access size	2018-08-20 20:37:57 +00:00
MSP430	…
Mips	[DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target.	2018-08-28 03:47:20 +00:00
NVPTX	[NVPTX] Implement isLegalToVectorizeLoadChain	2018-08-27 17:29:43 +00:00
Nios2	…
PowerPC	[PPC] Remove Darwin support from POWER backend.	2018-08-28 01:18:29 +00:00
RISCV	[RISCV] atomic_store_nn have a different layout to regular store	2018-08-27 07:08:18 +00:00
SPARC	[Sparc] Add support for the cycle counter available in GR740	2018-08-27 11:11:47 +00:00
SystemZ	[PPC] Remove Darwin support from POWER backend.	2018-08-28 01:18:29 +00:00
Thumb	[SelectionDAG] Improve the legalisation lowering of UMULO.	2018-08-16 18:39:39 +00:00
Thumb2	[SelectionDAG] Improve the legalisation lowering of UMULO.	2018-08-16 18:39:39 +00:00
WebAssembly	[WebAssembly][NFC] Fix up SIMD bitwise tests	2018-08-28 18:33:31 +00:00
WinCFGuard	Rename the cfguard module flag to cfguardtable	2018-08-10 09:48:53 +00:00
WinEH	…
X86	[X86][AVX] Prefer VPBLENDW+VPBLENDD to VPBLENDVB for v16i16 blend shuffles	2018-08-29 10:51:08 +00:00
XCore	[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)	2018-07-15 16:27:07 +00:00