forked from OSchip/llvm-project
144 lines
5.5 KiB
YAML
144 lines
5.5 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
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--- |
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define <4 x i32> @test_load_v4i32_noalign(<4 x i32>* %p1) {
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%r = load <4 x i32>, <4 x i32>* %p1, align 1
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ret <4 x i32> %r
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}
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define <4 x i32> @test_load_v4i32_align(<4 x i32>* %p1) {
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%r = load <4 x i32>, <4 x i32>* %p1, align 16
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ret <4 x i32> %r
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}
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define <4 x i32>* @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) {
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store <4 x i32> %val, <4 x i32>* %p1, align 16
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ret <4 x i32>* %p1
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}
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define <4 x i32>* @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) {
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store <4 x i32> %val, <4 x i32>* %p1, align 1
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ret <4 x i32>* %p1
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}
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...
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---
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# ALL-LABEL: name: test_load_v4i32_noalign
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name: test_load_v4i32_noalign
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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# ALL: - { id: 0, class: gr64, preferred-register: '' }
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# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' }
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# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' }
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- { id: 0, class: gpr }
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- { id: 1, class: vecr }
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# ALL: %0 = COPY %rdi
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# SSE: %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
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# AVX: %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
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# AVX512F: %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
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# AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
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# ALL: %xmm0 = COPY %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %rdi
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%0(p0) = COPY %rdi
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%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
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%xmm0 = COPY %1(<4 x s32>)
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RET 0, implicit %xmm0
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...
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---
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# ALL-LABEL: name: test_load_v4i32_align
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name: test_load_v4i32_align
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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# ALL: - { id: 0, class: gr64, preferred-register: '' }
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# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' }
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# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' }
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- { id: 0, class: gpr }
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- { id: 1, class: vecr }
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# ALL: %0 = COPY %rdi
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# SSE: %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
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# AVX: %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
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# AVX512F: %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
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# AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
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# ALL: %xmm0 = COPY %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %rdi
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%0(p0) = COPY %rdi
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%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1)
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%xmm0 = COPY %1(<4 x s32>)
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RET 0, implicit %xmm0
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...
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---
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# ALL-LABEL: name: test_store_v4i32_align
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name: test_store_v4i32_align
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' }
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# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' }
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# ALL: - { id: 1, class: gr64, preferred-register: '' }
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- { id: 0, class: vecr }
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- { id: 1, class: gpr }
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# ALL: %0 = COPY %xmm0
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# ALL: %1 = COPY %rdi
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# SSE: MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
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# AVX: VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
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# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
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# AVX512VL: VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
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# ALL: %rax = COPY %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %rdi, %xmm0
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%0(<4 x s32>) = COPY %xmm0
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%1(p0) = COPY %rdi
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G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16)
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%rax = COPY %1(p0)
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RET 0, implicit %rax
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...
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---
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# ALL-LABEL: name: test_store_v4i32_noalign
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name: test_store_v4i32_noalign
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' }
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# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' }
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# ALL: - { id: 1, class: gr64, preferred-register: '' }
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- { id: 0, class: vecr }
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- { id: 1, class: gpr }
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# ALL: %0 = COPY %xmm0
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# ALL: %1 = COPY %rdi
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# SSE: MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
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# AVX: VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
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# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
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# AVX512VL: VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
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# ALL: %rax = COPY %1
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body: |
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bb.1 (%ir-block.0):
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liveins: %rdi, %xmm0
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%0(<4 x s32>) = COPY %xmm0
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%1(p0) = COPY %rdi
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G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1)
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%rax = COPY %1(p0)
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RET 0, implicit %rax
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...
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