llvm-project/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir

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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Test that rules where multiple operands must be the same operand successfully
# match. Also test that the rules do not match when they're not the same
# operand.
---
name: test_blsr32rr
# CHECK-LABEL: name: test_blsr32rr
alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
# G_ADD and G_AND both use %0 so we should match this.
# CHECK: %3 = BLSR32rr %0
body: |
bb.1:
liveins: %edi
%0(s32) = COPY %edi
%1(s32) = G_CONSTANT i32 -1
%2(s32) = G_ADD %0, %1
%3(s32) = G_AND %2, %0
%edi = COPY %3
...
---
name: test_blsr32rr_nomatch
# CHECK-LABEL: name: test_blsr32rr_nomatch
alignment: 4
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
# G_ADD and G_AND use different operands so we shouldn't match this.
# CHECK-NOT: BLSR32rr
body: |
bb.1:
liveins: %edi
%0(s32) = COPY %edi
%1(s32) = G_CONSTANT i32 -1
%2(s32) = G_ADD %1, %1
%3(s32) = G_AND %2, %0
%edi = COPY %3
...