forked from OSchip/llvm-project
300 lines
12 KiB
C++
300 lines
12 KiB
C++
//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Hexagon uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
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#include "Hexagon.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/Target/TargetLowering.h"
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#include <cstdint>
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#include <utility>
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namespace llvm {
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namespace HexagonISD {
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enum NodeType : unsigned {
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OP_BEGIN = ISD::BUILTIN_OP_END,
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CONST32 = OP_BEGIN,
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CONST32_GP, // For marking data present in GP.
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ALLOCA,
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AT_GOT, // Index in GOT.
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AT_PCREL, // Offset relative to PC.
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CALL, // Function call.
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CALLnr, // Function call that does not return.
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CALLR,
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RET_FLAG, // Return with a flag operand.
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BARRIER, // Memory barrier.
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JT, // Jump table.
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CP, // Constant pool.
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COMBINE,
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PACKHL,
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VSPLATB,
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VSPLATH,
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SHUFFEB,
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SHUFFEH,
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SHUFFOB,
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SHUFFOH,
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VSXTBH,
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VSXTBW,
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VSRAW,
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VSRAH,
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VSRLW,
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VSRLH,
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VSHLW,
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VSHLH,
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VCMPBEQ,
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VCMPBGT,
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VCMPBGTU,
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VCMPHEQ,
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VCMPHGT,
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VCMPHGTU,
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VCMPWEQ,
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VCMPWGT,
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VCMPWGTU,
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INSERT,
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INSERTRP,
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EXTRACTU,
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EXTRACTURP,
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VCOMBINE,
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VPACK,
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TC_RETURN,
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EH_RETURN,
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DCFETCH,
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READCYCLE,
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OP_END
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};
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} // end namespace HexagonISD
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class HexagonSubtarget;
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class HexagonTargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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const HexagonTargetMachine &HTM;
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const HexagonSubtarget &Subtarget;
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bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
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const;
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void promoteLdStType(MVT VT, MVT PromotedLdStVT);
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public:
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explicit HexagonTargetLowering(const TargetMachine &TM,
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const HexagonSubtarget &ST);
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization. Targets which want to do tail call
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/// optimization should implement this function.
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bool IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
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bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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bool isTruncateFree(EVT VT1, EVT VT2) const override;
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bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
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/// Return true if an FMA operation is faster than a pair of mul and add
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/// instructions. fmuladd intrinsics will be expanded to FMAs when this
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/// method returns true (and FMAs are legal), otherwise fmuladd is
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/// expanded to mul + add.
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bool isFMAFasterThanFMulAndFAdd(EVT) const override;
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// Should we expand the build vector with shuffles?
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bool shouldExpandBuildVectorWithShuffles(EVT VT,
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unsigned DefinedValues) const override;
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT)
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const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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SDValue
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG) const;
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SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG) const;
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SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG) const;
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SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
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GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT,
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unsigned ReturnReg, unsigned char OperandFlags) const;
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SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals,
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const SmallVectorImpl<SDValue> &OutVals,
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SDValue Callee) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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bool CanLowerReturn(CallingConv::ID CallConv,
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MachineFunction &MF, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SDLoc &dl, SelectionDAG &DAG) const override;
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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unsigned
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getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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return Hexagon::R0;
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}
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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unsigned
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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return Hexagon::R1;
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}
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
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EVT VT) const override {
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if (!VT.isVector())
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return MVT::i1;
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else
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return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
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}
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bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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unsigned
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode == "o")
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return InlineAsm::Constraint_o;
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return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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}
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// Intrinsics
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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/// The type may be VoidTy, in which case only return true if the addressing
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/// mode is legal for a load/store of any legal type.
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/// TODO: Handle pre/postinc as well.
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
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Type *Ty, unsigned AS) const override;
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/// Return true if folding a constant offset with the given GlobalAddress
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/// is legal. It is frequently not legal in PIC relocation models.
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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/// isLegalICmpImmediate - Return true if the specified immediate is legal
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/// icmp immediate, that is the target has icmp instructions which can
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/// compare a register against the immediate without having to materialize
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/// the immediate into a register.
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bool isLegalICmpImmediate(int64_t Imm) const override;
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
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unsigned Align, bool *Fast) const override;
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/// Returns relocation base for the given PIC jumptable.
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SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
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const override;
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// Handling of atomic RMW instructions.
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Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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AtomicOrdering Ord) const override;
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Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
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Value *Addr, AtomicOrdering Ord) const override;
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AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
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bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
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bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
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AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
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return AtomicExpansionKind::LLSC;
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}
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protected:
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
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const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
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