forked from OSchip/llvm-project
3cb7e7bf95
For the test case in this patch like below
struct t { int a; } __attribute__((preserve_access_index));
int foo(void *);
int test(struct t *arg) {
long param[1];
param[0] = (long)&arg->a;
return foo(param);
}
The IR right before BPF SimplifyPatchable phase:
%1:gpr = LD_imm64 @"llvm.t:0:0$0:0"
%2:gpr = LDD killed %1:gpr, 0
%3:gpr = ADD_rr %0:gpr(tied-def 0), killed %2:gpr
STD killed %3:gpr, %stack.0.param, 0
After SimplifyPatchable phase, the incorrect IR is generated:
%1:gpr = LD_imm64 @"llvm.t:0:0$0:0"
%3:gpr = ADD_rr %0:gpr(tied-def 0), killed %1:gpr
CORE_MEM killed %3:gpr, 306, %0:gpr, @"llvm.t:0:0$0:0"
Note that CORE_MEM pseudo op is introduced to encode
memory operations related to CORE. In the above, we intend
to check whether we have a store like
*(%3:gpr + 0) = ...
and if this is the case, we could replace it with
*(%0:gpr + @"llvm.t:0:0$0:0"_ = ...
Unfortunately, in the above, IR for the store is
*(%stack.0.param + 0) = %3:gpr
and transformation should not happen.
Note that we won't have problem if the actual CORE
dereference (arg->a) happens.
This patch fixed the problem by skip CORE optimization if
the use of ADD_rr result is not the base address of the store
operation.
Differential Revision: https://reviews.llvm.org/D78466
|
||
|---|---|---|
| .. | ||
| BTF | ||
| CORE | ||
| 32-bit-subreg-alu.ll | ||
| 32-bit-subreg-cond-select.ll | ||
| 32-bit-subreg-load-store.ll | ||
| 32-bit-subreg-peephole-phi-1.ll | ||
| 32-bit-subreg-peephole-phi-2.ll | ||
| 32-bit-subreg-peephole-phi-3.ll | ||
| 32-bit-subreg-peephole.ll | ||
| alu8.ll | ||
| atomics.ll | ||
| basictest.ll | ||
| byval.ll | ||
| callx.ll | ||
| cc_args.ll | ||
| cc_args_be.ll | ||
| cc_ret.ll | ||
| cmp.ll | ||
| dwarfdump.ll | ||
| elf-symbol-information.ll | ||
| ex1.ll | ||
| fi_ri.ll | ||
| i128.ll | ||
| inline_asm.ll | ||
| inlineasm-output-template.ll | ||
| intrinsics.ll | ||
| is_trunc_free.ll | ||
| is_zext_free.ll | ||
| lit.local.cfg | ||
| load.ll | ||
| loops.ll | ||
| many_args1.ll | ||
| many_args2.ll | ||
| mem_offset.ll | ||
| mem_offset_be.ll | ||
| memcpy-expand-in-order.ll | ||
| objdump_atomics.ll | ||
| objdump_cond_op.ll | ||
| objdump_cond_op_2.ll | ||
| objdump_imm_hex.ll | ||
| objdump_intrinsics.ll | ||
| objdump_static_var.ll | ||
| objdump_trivial.ll | ||
| objdump_two_funcs.ll | ||
| optnone-1.ll | ||
| reloc-btf-2.ll | ||
| reloc-btf.ll | ||
| reloc.ll | ||
| remove_truncate_1.ll | ||
| remove_truncate_2.ll | ||
| remove_truncate_3.ll | ||
| remove_truncate_4.ll | ||
| remove_truncate_5.ll | ||
| remove_truncate_6.ll | ||
| rodata_1.ll | ||
| rodata_2.ll | ||
| rodata_3.ll | ||
| rodata_4.ll | ||
| sanity.ll | ||
| sdiv_error.ll | ||
| select_ri.ll | ||
| setcc.ll | ||
| shifts.ll | ||
| sockex2.ll | ||
| struct_ret1.ll | ||
| struct_ret2.ll | ||
| undef.ll | ||
| vararg1.ll | ||
| warn-call.ll | ||
| warn-stack.ll | ||
| xadd.ll | ||
| xadd_legal.ll | ||